Posted on May 17, 2011 at 13:40 /* -----------------------------------------------------------------------
TIM3 Configuration: generate 4 PWM signals with 4 different duty cycles:
TIM3CLK = 36 MHz, Prescaler = 0x0, TIM3 counter clock = 36 MHz
TIM3 ARR Register = 999 => TIM3 Frequency = TIM3 counter clock/(ARR + 1)
TIM3 Frequency = 36 KHz.
TIM3 Channel1 duty cycle = (TIM3_CCR1/ TIM3_ARR)* 100 = 50%
TIM3 Channel2 duty cycle = (TIM3_CCR2/ TIM3_ARR)* 100 = 37.5%
TIM3 Channel3 duty cycle = (TIM3_CCR3/ TIM3_ARR)* 100 = 25%
TIM3 Channel4 duty cycle = (TIM3_CCR4/ TIM3_ARR)* 100 = 12.5%
----------------------------------------------------------------------- */
/* Time base configuration */
TIM_TimeBaseStructure.TIM_Period = 999;
TIM_TimeBaseStructure.TIM_Prescaler = 0;
TIM_TimeBaseStructure.TIM_ClockDivision = 0;
TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
TIM_TimeBaseInit(TIM3, &TIM_TimeBaseStructure);
/* PWM1 Mode configuration: Channel1 */
TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;
TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
TIM_OCInitStructure.TIM_Pulse = CCR1_Val;
TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
TIM_OC1Init(TIM3, &TIM_OCInitStructure);
TIM_OC1PreloadConfig(TIM3, TIM_OCPreload_Enable);
Above is example from TIM PWM generation.
For TIM 2-7 Max freq = 36MHz, TIM 1,8 Max freq = 72MHz
TIM freq = 72 or 36MHz divided by (ARR+1),
so when you run ARR with 0,1,2,3,4,.... it cannot generate 26MHz or 13MHz precisely. I think we might need to change crystal or oscillator from default 8 MHz to do that but it might effect other peripheral such as USB, ethernet, etc.
For interface Max9851, Now I tried to change oscillator I can find in my country but it's not 13MHz or 26MHz It's close to but not exactly. After that I got ULK bit in status 0 register set. It means that DAC PLL is not locked because of MCLK wrong freq (I guess). So I give up, I might try again when I order the correct oscillator from digikey next time. Be aware that there are many kind of oscillator if you got 0.8V Peak2Peak like me, it's not work with this MCLK requirement.
(Digital input MCLK need VIH and VIL accord to its data sheet, so it's safer to use oscillator that has VOL = 10%VDD and VOH = 90%VDD for example) Thus, 644-4086-1-ND or 644-1089-1-ND are not work, and you will get Analog part is not ready like me (AOK = 0, in status 1 register)
