Max internal clock for STM32F7 timers

[mminuti9]

Posted on November 09, 2016 at 14:58

Hi all,

           I'm evaluating STM32F765 uc for my application and I need to clarify how the GP Timers are clocked.In other words, at page 38 of product datasheet, for TIM3 is wrote: Max Interface clock = 54MHz, Max Timer clock = 108/216 MHz.What's the difference between ''Interface'' and ''Timer'' clock? What's the maximum frequency I can use to clock the timer? 108 or 216 MHz?Thanks in advance for your support.Maurizio #stm3235f765-clock-timers

[Walid FTITI_O]

Posted on November 10, 2016 at 14:30

Hi 

mauri1106,

The timers connected to APB2 are clocked from TIMxCLK up to 216 MHz, while the timers connected to APB1 are clocked from TIMxCLK either up to 108 MHz or 216 MHz depending on TIMPRE bit configuration in the RCC_DCKCFGR register:

When TIMPRE bit in the RCC_DCKCFGR1 register is set, if APBx prescaler is 1,2 or 4, then TIMxCLK = HCLK, otherwise TIMxCLK = 4x PCLKx

-Hannibal-

[slimen]

Posted on November 10, 2016 at 14:32

Hello,

The maximum timer clock is depends on TIMPRE bit configuration in the RCC_DCKCFGR register: when the APB prescaler is configured to adivision factor of 1, the timer clock frequencies are set totwice to the frequency of the APB domain to which the timers are connected:TIMxCLK = 2xPCLKx.Thus, when the APB prescaler is configured to adivision factor of 1, 2 or 4, the timer clock frequencies are setto four times to the frequency of the APB domain to which the timers are connected:TIMxCLK = 4xPCLKx.You have to check the reference manual 

http://www.st.com/content/ccc/resource/technical/document/reference_manual/group0/96/8b/0d/ec/16/22/43/71/DM00224583/files/DM00224583.pdf/jcr:content/translations/en.DM00224583.pdf

 for more clarification.Regards