LSI Clock compensation issue, technical datas ?

[F-MA-1]

Hello,

I'm working on a low cost design which use LSI Clock. I need to compensate RC osc. deviation as best as possible.

I didn't find technical datas about this. Is there any documents with precise datas on deviations according Temp. for examples and others factors ? Or where can I find FAE contact ?

Many Thanks,

[waclawek.jan]

Which STM32?

Generally, in STM32, LSI is designed to be very low consumption, which also means that it's low precision and there's no better characterization than what you find in the datasheet.

For higher precision, you have to resort to other means of timing.

JW

[F-MA-1]

Oups ... it's on STM32L031 chip.

Yes you're right for higher precision, other solution would be great ...

For now Low cost and Low consumption determined the LSI use.

I hope ST made some characterization on this, a bit more than in public datasheet ...

Thanks for your back JW

[TDK]

> I hope ST made some characterization on this, a bit more than in public datasheet ...

What exactly are you hoping for? The huge range is because LSI is not precise. You could calibrate it on a chip by chip basis. Still going to have the temperature dependence and possibly long term drift as well. There aren't great options for turning a low precision timer into a high precision one.

[F-MA-1]

Frequency drift is given for 0 - 85°. I don't know if I can find characterization for LSI around 25°C (+/-15°C) - Deviation according T° as data below for HSI on datasheet.

 

Note : On LSI characteristics, datasheet and ref manual give 2 values on LSI typ. value : 38KHz and 37KHz ... which value is correct ?

[PJadh.1]

Hi there @TDK​ , recently I also stumbled upon the same query asked by @F-MA-1​ . What is the average value to consider while working with LSI?

Application - I want to set my wwdg and iwdg on my application. I find Iwdg is nice to have watchdog in applications which are safety related since it relies on LSI clock.

The wwdg looks quite reliable, since it relies on the HSI which has less than >1% accuracy. But I am afraid the values given in chart for LSI Oscillator Characteristics does not look good. There is deviation from 26Khz - 56 Khz (which is suppose to 37Khz or 38Khz). I want to avoid the false positive problems because of the iwdg reset.

My question -

1. Is it possible that some of the MCU shipped by ST will have LSI having 56Khz or 26Khz which was supppose to be 37-38Khz?

2. What frequency should I consider for worst scenario when configuring reload value iwdg? SHould I consider 56khz? which almost doubles the reload value.

[TDK]

> What is the average value to consider while working with LSI?

I'm not working with any more information than what you have. The range of 26-65 kHz is wide. If you want a more precise value, I would characterize and calibrate it on a chip by chip basis.

> Is it possible that some of the MCU shipped by ST will have LSI having 56Khz or 26Khz which was supppose to be 37-38Khz?

That's what the datasheet says. Realistically, I would imagine it has a normal distribution without many outliers on either end. I would expect the range at ambient temperature is narrower than the full range. Again, just an educated guess based on experience. I don't have inside info.

> What frequency should I consider for worst scenario when configuring reload value iwdg? SHould I consider 56khz? which almost doubles the reload value.

26 kHz or 56 kHz per the datasheet, whichever you consider "worst".

[PJadh.1]

For iwdg. higher the frequency the faster the count down of the counter so it has more chances of triggering the false positive. Worst case - design the iwdg keeping in mind the frequency is 56Khz. Thanks for reply though.

I hope I get some insights from the @ST Community​ @Community Admin​ 

[Tesla DeLorean]

I don't see them providing extra-datasheet information.

The barn door is purposely wide as it likely depends on voltage, temperature, diffusion of N/P transistors and poly-silicon.

The watchdog is really for catastrophic code/system failure, you should keep tasks in check with more accurate timers and counters, and track the LSI performance at that level.

You should perhaps cycle some devices in a temp chamber, conclude how poor performance is, and lack of any meaningful way of pulling the frequency to compensate for variables you can measure.