To give you an update to the LSE crystal oscillator startup issue with the STM32H743XIH6, we have made some more investigations and this is what we have found.
There was a problem with the software, that we found. If we made a Backup Domain reset before initialising the RTC, the xtal started up okay. Even with the external load capacitors CL1 = CL2 = 4.7pF. The crystal that we are using is the Abracon ASB07.32.768KHZ-7-T which have a CL of 7pF.
The Backup Domain reset is in order to clear the Clock Security System LSECSSD flag. If this flag is set, the LSE clock is no longer propagated to the RTC and the system. This is according the Errata document for the STM32H743. We have also seen that this also affects the startup of the crystal as well. When this flag was set the amplitude of the xtal was lower and the crystal startup was longer as compared to when the flag was reseted.
We also noticed that when the microcontroller is booted up, this LSECSSD flag is already set, even when the CSS on the RTC is not enabled. At the moment we cannot explain this.
As can be seen, we see that the amplitude of the oscillations are increasing up to a point of stable frequency as expected. Okay, the amplitude is very small but this could be due to the 10pF oscilloscope probe, because we see the RTC clock counting up okay.
Dark Blue = OSC32_IN
As can be seen, the 3.0V voltage supply is asserted after the push button has been pressed and is constant over the oscillation “Dip�?.
With regards to this "Dip" in oscillations, we are still trying to track this down to find out what is causing this. Here is a closer look at the oscillation "Dip". It appears that after approximately 180ms something affects the LSE crystal oscillator.
Best regards,
Matthew
