2016-12-07 10:37 AM
I've got a development board based on the STM32F746 from Mikroelektronika. The board has a 32.768 kHz crystal connected to the LSE oscillator pins. I can't get the oscillator to start and come ready.
Here's my code--any idea what I'm doing wrong?
/*
* Start the LSE (32 kHZ) oscillator
*/
RCC->APB1ENR |= RCC_APB1ENR_PWREN; // enable PWR interface clock
PWR->CR1 |= PWR_CR1_DBP; // disable backup domain write protection
RCC->BDCR |= RCC_BDCR_BDRST; // reset backup domain
RCC->BDCR &= ~RCC_BDCR_BDRST; // deassert backup domain reset
RCC->BDCR |= RCC_BDCR_LSEON; // enable LSE oscillator
while(!(RCC->BDCR & RCC_BDCR_LSERDY))
; // wait for LSE ready
RCC->BDCR &= ~(0b11 << 8); //
RCC->BDCR |= 0b01 << 8; // select LSE as RTC clock
RCC->BDCR |= RCC_BDCR_RTCEN; // enable RTC
2016-12-07 11:06 AM
How do you know that LSE is not running?
Have a look also at
https://community.st.com/0D50X00009XkaBaSAJ
JW
2016-12-07 11:19 AM
Does the F7 have the write buffer hazard with respect to you enabling a clock, and then immediately trying to write to the peripheral? (Check Errata)
I'd probably fence those first two writes.
2016-12-07 01:21 PM
Hi Jerry,
as usual I'm going to advise you to use the STM32CubeMX tool. The code should be functional. Try to run it, and if it works, compare your code with the one generated with yours + check the ref manual etc. for details why it's done this way etc...
Good luck,
Renegade
2016-12-07 02:17 PM
I don't know whether it's actually running. I'm inferring that it is if the LSERDY bit in the BDCR register comes on. I never see this bit getting set--the while loop never exits.
2016-12-07 02:17 PM
I don't think that's the problem. The issue persists even when I single-step the code in the debugger.
2016-12-07 02:29 PM
This I'll presume is with
Mikroelektronika's MikroC? Is it handling the volatile nature of peripheral registers properly? Can you turn optimization off?
2016-12-07 02:52 PM
No, it's Rowley Crossworks with GCC. I checked and all the peripheral registers related to this issue are properly declared volatile. All optimizations are off.
2016-12-07 02:57 PM
And does LSERDY assert in BDCR or not? What I'm reading suggests you see it in the debugger, but not your loop.
If you never see LSERDY assert you need to look at the external hardware, and probe with a scope, or pipe LSE to MCO or TAMPER, or wherever it gets emitted on the F7.
If LSERDY asserts in the register but your code doesn't see it, then you'll need to review a disassembly of the offending code to understand why.
2016-12-07 03:12 PM
LSERDY never asserts in BDCR. Time to probe with a scope... Just wanted to make sure first that I wasn't doing something stupid in the code. I have very similar code for a few STM32F4 boards I have and it works just fine on them.