2020-10-10 12:34 AM
dear all,
My question is about the Cortex-M0+ options that were selected for the STM32G0 products (table 1-1 from the ARM Cortex-M0+ TRM). I can hardly find them in the STM32G0 RM and DS. Do you know where I can find the answer ?
Regards
2020-10-14 07:36 AM
Hello @BMUSS.1 ,
Welcome to STM32 Community.
The Cortex®-M0+ technical reference manual contains information related to Arm® Cortex®-M0+ core.
Although, the STM32G0 reference manuals as RM0444 and RM0454 providing information related to the STM32G0 microcontrollers, and the complements datasheets detailed the features available, ordering information, pin assignment, electrical characteristics and packaging..
Please, don’t hesitate to ask me for more clarification.
Imen
2020-10-18 03:05 AM
Dear Imen,
Thanks for your valuable feedback. In fact I wanted to know more about the options that were chosen by ST for the integration of Cortex-M0+. ARM offers a wide range of options in order to optimize the gate count. It includes the number of breakpoints, watchpoints, the MPU, the number of IT and the implementation of the privileged/unprivileged mode. It seems that ST has picked all of these options to cover as manyuse cases as possible.
regards
2020-10-18 05:21 AM
ST also has Programming Manuals describing core side details.
Can you not pull some details from the ROM Tables?
2020-10-18 06:33 AM
https://developer.arm.com/documentation/ddi0314/h