2012-11-24 06:09 AM
Hi,
please have a look at the following code (STM32F407):volatile long long vllPosition;
void TIM1_UP_TIM10_IRQHandler(void){ ... do interrupt stuff ... vllPosition ++; ... do interrupt stuff ... } int main( void){ ... do some init stuff ... for(;;){ ... do the loop stuff ... if( ...){ // from time to time it is necessary to assing some value to llPosition vllPosition= llSomeValue; } ... do the loop stuff ... } } As long long is 64 bit, the access to vllPosition is non-atomic. So an assignment like vllPosition= llSomeValue is dangerous: it might be interrupted by my interrupt and then the complete thing will mix up. In an easy access, I would like to disable the interrupt temporarily. There would be 3 different possibilities I see: 1.:NVIC_DisableIRQ( TIM1_UP_TIM10_IRQn);
vllPosition= llSomeValue; NVIC_EnableIRQ( TIM1_UP_TIM10_IRQn); 2. (The TIM1_UP_TIM10_IRQ is entered exclusively by the UIE):TIM1->DIER = 0;
vllPosition= llSomeValue; TIM1->DIER = TIM_DIER_UIE; 3.__disable_irq();
vllPosition= llSomeValue; __enable_irq(); Is any of these methods 100% safe (of course I would prefer method 1 or 2, as 3 disables all interrupts)? (Due to the prefetch delay I am not sure about this - I did not find a guarantee anywhere and it is difficult to decide only by testing). (Or would I need some more elaborate methode to ensure this in a secure way, e. g. with semaphores or so?) #stm322012-11-24 08:00 AM
I found it meanwhile in the ARM docs:
The Disable in (1.) needs an additional ISB and DSB instruction, see
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dai0321a/BIHHFHJD.html
(''4.6 Disabling Interrupts using NVIC'')The Disable in (2.) is NOT recommended, see
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dai0321a/BIHHFHJD.html
(''4.9 Disabling interrupts at peripherals'')The Disable in (3.) works without ISB and DSB - but of course it stops all interrupts:
siehe:http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dai0321a/BIHHFHJD.html
(''4.8. Disabling interrupts using CPS and MSR instructions'')