LL_TIM_EnableDMAReq_CC1 triggers DMA correctly, LL_TIM_EnableDMAReq_UPDATE does not.

[Johi]

I made an application that uses burst DMA on T2 of an STM32F407VET6 to create morse code pulses as a challenge for Burst DMA..

My strategy is to write to ARR, the reserved register in between and CCR1 to make pulses of various width and duty cycle as 1 burst. This works as long as I trigger my DMA with LL_TIM_EnableDMAReq_CC1, once I change to LL_TIM_EnableDMAReq_UPDATE dma does not longer kick in and registers stay the same.

I wonder why?

(IMHO Update comes every time T2 reaches ARR and goes to 0, so T2 should trigger a burst from the dma to fill TIMx_ARR, the reserved register and CCR1 as well. Attached detailed case file with scope printscreens and source code.) 

[waclawek.jan]

Read our and check/post TIM and relevant DMA registers content.

JW

[Johi]

The only (IMHO) relevant difference is DIER where UDE or CC1DE is 1 but that is quite obvious as this is the objective of the program. It seems that DMA request are not sent by TIM to DMA controller, but I have no idea why.

The fact that DMAR has different values is the result rather than the source of the problem.

I added all DMA1 registers and TIM2 to the document (see chapter 6-7-8-9 of the attached document)

Below TIM2 in the case where UDE does not start DMA cycle (but TIM2-ISR-UIF is still called many times?).

[waclawek.jan · Accepted solution]

DMA1 Stream5 has no trigger from TIM2_UP:

JW

[Johi]

@waclawek.jan thank you very much for the solution, when I read 10.3.3. in RM0090, i interpreted the text as channal for data not for trigger. Afterwards i found out that all DMA passes via DMAR for timer in burst mode. But it did not cross my mind that my reading of 10.3.3. was also wrong. Again much appreciation for your support to the forum.