2025-02-23 6:33 PM
Other chips have the erratum "Transmit data FIFO is corrupted when a write sequence to the FIFO is interrupted with accesses to certain OTG_HS registers" (eg ES0392 2.25.2 for STM32H743).
It isn't listed in the ES0596 rev5 errata for STM32H7Rxx/7Sxx - are those devices unaffected, or it just hasn't been listed there? Thanks.
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2025-02-24 7:55 AM
Hi @mkj & welcome to ST Community
According to current errata sheet, this erratum is not applicable. Note that enabling DMA mode guarantees FIFO write sequence is not interrupted.
To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.
2025-02-24 7:55 AM
Hi @mkj & welcome to ST Community
According to current errata sheet, this erratum is not applicable. Note that enabling DMA mode guarantees FIFO write sequence is not interrupted.
To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.