They don't make DRAM QSPI chips in an SO-8 package with more than 64 Mbits (maps to 2 Mbytes * 32). Given the current processor shortage, I've got an application where I'd like more memory (and I'm using a 100 pin package which is quite pin limited, so no FMC for this). I think I can beat up the design to free all the OSPI pins, but just a simple add of the chip, using the high order bits and paralleling CS (perhaps) and the clock doesn't seem as if it would work.
Not sure if the processor OSPI subsystem can handle it, since (AFAIK), an OSPI SDRAM chip is not necessarily two QSPI chips in the same package.... or is it?
Can it be done? Anybody ever try it? That would allow a flash/SDRAM combination or just FLASH or SDRAM.
Not going to try using BGA chips, can't handle them.
Any ideas?
