Interrupt priority clarification

[longchair]

Posted on November 02, 2012 at 14:51

Hello guys,

I have been messing with interrupts recently and I have hard time to find in the manuals how the priorities actually work. I have seen the priority groups and priority values. If I understood it properly, lower priorities will give the higher priority level. Though to put it in a simple situation. lets says That I have and interrupt that 'll call IRQ1 here coming every 100ms and that it's processing is lasting 20ms. Now lets say that I have an other IRQ called IRQ2 coming every 5 millisecond and lasting 1ms. If IRQ2 has a higher priority than IRQ1, does this mean that IRQ2 can be fired several times withing the processing of IRQ1 ? when IRQ2 is finished within IRQ1 processing, is IRQ1 processing resumed ? If you have further links describing the whole priority concept, thanks to point them out. I have looked into both reference manual and programming manual, but that doesn't look very clear to me :) Thanks for any clarification. Lionel #nvic

[jpeacock2399]

Posted on November 02, 2012 at 19:02 With nested interrupts a higher priority (lower interrupt level) interrupt request will preempt a lower priority interrupt service routine.  So if (for example) you set TIM1 interrupts at level 3, and TIM8 interrupts at level 2, the TIM8 interrupts will preempt the TIM1 service routines.  You need to make sure your stack is large enough to accomodate all the interrupt service routines that can be active when nesting. You might also want to read about tail-chaining.  It reduces overhead in nested interrupts by deferring the register pops off the stack. ST doesn't provide much information on the NVIC interrupt controller because it's part of the Cortex M core.  You need to look at the ARM manuals for information on programming interrupt priorities.   Jack Peacock