Interrupt handling scheme

[drobison]

Posted on September 24, 2012 at 19:07

I've spent some time with the stm32 manual, but there is always very crucial details omitted.  I've been using a st10 and thinking of upgrading.  The ST10 handled interrupts in a peculiar way I think.  It had two different types of interrupts.  One was a peripheral event controlled transfer and one was a normal interrupt service routine.  Being in an interrupt service routine of level x meant that any interrupt of level x of lower was completely ignored and never serviced.  A peripheral event of lower level and group would be serviced after the higher one was done.

This was nowhere in the manual.  I had to figure this out through trial and error.  Does the stm32 go back after that higher level interrupt service routine is completed and check if any other interrupts asked to be serviced, and service them?  Is there something like a peripherial event controller (PEC) in the stm32 that allows it to just move around a word from a predefined source and destination instead of interrupting the CPU and changing the priority level? Is there a document that goes into detail about this stuff?  Which page is it on? #interrupt-handling-pec

[Tesla DeLorean]

Posted on September 24, 2012 at 19:43

Download an ARM Cortex-M3 manual, and review the documentation of the NVIC (Nested Vectoring Interrupt Controller) embedded in/with the core.

See also Joseph Yiu's fine books on the Cortex-M3, and M0 series parts for a more practical application.

[frankmeyer9]

Posted on September 24, 2012 at 20:08

I would follow clive's advice, and download a Cortex M3 manual from the ARM website, in addition to the STM32 manual.

The NVIC, the 'core' of the interrupt processing, is basically identical on all equivalent devices. The differences are minor, such as the number of interrupt priorities. In comparision to the ST10 (as you describe) and the PIC18F for example, the interrupt handling on the Cortex M is fairly uniform and more of a pleasure to work with.Is there something like a peripherial event controller (PEC) in the stm32 that allows it to just move around a word from a predefined source and destination instead of interrupting the CPU and changing the priority level? DMA.Is there a document that goes into detail about this stuff?  Which page is it on? In general, the Cortex M<x> documentation on the ARM website, covering core details, and vendor documentation (say: ST), which rather describes implementation-specifics. To learn about ARM Cortex family, the ARM manuals are generally a recommended reading.

[Barry.Richard]

Posted on September 25, 2012 at 12:16

The nested vectored interrupt controller (NVIC) is part of the Cortex-M core itself, and therefore part of the ARM documentation as others have already pointed out.

The NVIC implements a lot of clever features, such as late arriving, tail chaining, simple nesting, etc., but really you don’t need to know about any of that stuff to use it.To use the NVIC you need to first understand a few things about its behaviour, then just know which library function calls to use.  ST and ARM provide some simple API functions that hide most of the complexity for you.The things you need to know up front are:1) The lower the value you assign to an interrupt priority, the higher the priority of the interrupt is.  For example, 0 is the highest priority possible, 1 has a lower priority than 0, and 2 has a lower priority than 1.2) What the lowerst priority is.  This is the only thing that changes between different Cortex-M manufacturers.  On STM32 parts the lowest priority is 15.Regards,Richard (

http://www.FreeRTOS.org

)