Interpretation of SPI communication error

[Gpeti]

Hello,

Still struggling with my SPI setup.See https://community.st.com/s/feed/0D53W000006r3jX for details on SPI and GPIO settings.

On the exact same setup I have sometimes a correct communication and trace is :

SCK in yellow, MISO in blue. I send bytes 0xF0 0xDE from Slave to Master in simplex mode.

Then sometimes I have the following:

It looks like the signal is "in advance" compared to the clock. The first two bytes are missing but apart from that the bits are correct.

spi_pclk is 50MHz and SCK is 12.5MHz.

Do you have any idea what could cause this ?

I think an underrun at slave side cannot provoke this (I cannot detect the UDR event properly since due to the errata of SPI, I have to disable SPI between send and receive phases).

I made me wonder something else: what happens if the slave (in transmit only mode) writes into the TxFIFO while the clock is running ? I mean: when exactly a new byte or word (freshly written to the FIFO) is copied in the shift register ?

[TDK]

Could be explained by some spurious pulses on the SCK line prior to the transaction. Are you setting a CS pin for each transaction or do you just keep it low?

[Gpeti]

Makes sense however shouldn't it be visible on the trace ?

I don't use the CS (unfortunately, not my choice, I'm developping a simulator for a future product and I have to stick to the product behaviour). SSM=1. Not used at all at slave side.

It is a bit of a nightmare to make sure the slave simulator software is always ready to respond to the master.

[TDK]

It may have happened long before your scope trace started. Without using CS, you’ll have to take steps to ensure the master and slave are in sync. Perhaps detect delays of more than X ms on the slave side and interpret as a CS cycle.

[Gpeti]

"It may have happened long before". Indeed. Good point