Posted on December 25, 2017 at 19:00 The manuals mention 'ART accelerator allowing 0-wait state execution'.
That's a marketing lie of course - 0 waitstate only if all jumps are matched by entries in the jumpcache and the linear part of code contains enough single-(half)word instructions. This is rougly fulfilled with simple code with lots of local loops -- which is what's most benchmarks are all about.
There's also interaction with constants memory and data memory and other bus masters activities etc.etc.
Would code copied to RAM run faster?
Execution through S bus is slower than through I bus, so you may want to remap the SRAM to boot position when executing from it.
One of the short lived Technical Updates contained an interesting analysis of execution times vs. various mapping options.
Do all STM32 models run off the internal flash atmaximumspeed?
AFAIK only F4 and F7 through TCM has ART.
JW
