2019-09-09 01:29 AM
Hi friends, i am capturing frequency using timer pins(Input capture mode).
MCU = stm32f103c8t6
Software = Keil uvision 5
Debugger = st-link v2
I am getting this issue only when i use other timers except timer 1.
code is given below (Register level language)...
#include "stm32f10x.h"
int main()
{
RCC->APB1ENR |=RCC_APB1ENR_TIM2EN;
TIM2->PSC=7199;
TIM2->CCMR1 |=TIM_CCMR1_CC1S_0; // set T2[1] as input capture
TIM2->CCER &=~TIM_CCER_CC1P; // Rising edge
TIM2->CCMR1 &=~TIM_CCMR1_IC1PSC; // Diabling the PSC
TIM2->DIER |=TIM_DIER_UIE|TIM_DIER_CC1IE;
TIM2->CCER |=TIM_CCER_CC1E;
TIM2->CR1 |= TIM_CR1_CEN;
NVIC_EnableIRQ(TIM2_IRQn);
while(1)
{
// Not entering to while loop??
}
}
// Interrupt handler
void TIM2_IRQHandler(void)
{
if ((TIM2->SR & TIM_SR_CC1IF) != 0)
{
if ((TIM2->SR & TIM_SR_CC1OF) != 0) /* Check the overflow */
{
/* Overflow error management */
gap = 0; /* Reinitialize the laps computing */
TIM2->SR &= ~(TIM_SR_CC1OF | TIM_SR_CC1IF); /* Clear the flags */
}
if (gap == 0) /* Test if it is the first rising edge */
{
counter0 = TIM2->CCR1; /* Read the capture counter which clears the
CC1ICF */
gap = 1; /* Indicate that the first rising edge has yet been detected */
}
else
{
counter1 = TIM2->CCR1; /* Read the capture counter which clears the
CC1ICF */
if (counter1 > counter0) /* Check capture counter overflow */
{
Counter = counter1 - counter0;
Frequency=10000/Counter;
RPM=(Frequency*60)/4;
}
else
{
Counter = counter1 + 0xFFFF - counter0 + 1;
Frequency=10000/Counter;
RPM=(Frequency*60)/4;
}
counter0 = counter1;
}
}
else
{
/* Unexpected Interrupt */
/* Manage an error for robust application */
}
}
I think there is a mistake in my code in interrupt handler, kindly guide me friends to solve the issue.
Solved! Go to Solution.
2019-09-09 06:09 AM
You enable Update Interrupt
TIM2->DIER |=TIM_DIER_UIE|TIM_DIER_CC1IE;
but you then don't manage it (clear its flag) in the ISR.
JW
2019-09-09 06:09 AM
You enable Update Interrupt
TIM2->DIER |=TIM_DIER_UIE|TIM_DIER_CC1IE;
but you then don't manage it (clear its flag) in the ISR.
JW
2019-09-10 10:56 PM
Thank you waclawek, rightly spot
After clearing the flag it works fine.