The MDF FIFO is set to 24 bits like CIC output can be extended to 26 bits. Then, to fit with FIFO it's mandatory to use the SCALE block.
In case you enabled the INT block after CIC + SCALE blocks, then there is no possibility to adjust the output size from 26 bits to 24 bits.
I use the B-U585I-IOT02A, modified VREF+ pin to be powered from internal VREFBUF 1.5V. Then I use the DAC1 to produce a sine wave, it gets quite close to the rails.
The offset of the oscilloscope is around 35mV:
Then I sample the signal with the ADC1 from PA4, also using 1.5V as reference voltage using a pretty plain setup (no oversampling etc) and feed it to the MDF.
When I use the CIC stage with SINC5 and a decimation of 4, this should result in 24bit wide internal results.
Which gives a nice sine wave. However, if I use the same setup with decimation 5 then the internal results are 25.6bits wide - which is ok according to the datasheet - and I get this:
To get this, I had to switch off the SATuration interrupt.
Hello @Andreas Köpke,
From your inputs, here are my comments:
I will reproduce on my side but I don't expect an issue with the MDF. I come back with further analysis.
Thank you for sharing the details.
I'm referring to the Reference Manual
STM32U575/585 Arm®-based 32-bit MCUs
March 2022, RM0456 Rev 3, page 1239
where it says:
with N = 5, D = 4 and DSin = 14 this results in
DScic = 24
and with N = 5, D = 5 and DSin = 14 this results in
DScic = 25.60964
Both values are within the recommendation DScic < 26bit.