Improve bitbang driver speed
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‎2014-11-24 12:06 PM
Hi,
I am using the STM32F2xx cube API to implement a raw bitbang usb driver for the FTDI ft245. I am currently achieving speed of 5000 bytes/s. I would like to improve the speed. The bitbang code is simple as:<..>__disable_irq();// set data pins HAL_GPIO_WritePin(FT_D0_PORT, FT_D0_PIN, (CHECK_BIT(data, 0) == 0) ? GPIO_PIN_RESET : GPIO_PIN_SET); HAL_GPIO_WritePin(FT_D1_PORT, FT_D1_PIN, (CHECK_BIT(data, 1) == 0) ? GPIO_PIN_RESET : GPIO_PIN_SET); HAL_GPIO_WritePin(FT_D2_PORT, FT_D2_PIN, (CHECK_BIT(data, 2) == 0) ? GPIO_PIN_RESET : GPIO_PIN_SET); HAL_GPIO_WritePin(FT_D3_PORT, FT_D3_PIN, (CHECK_BIT(data, 3) == 0) ? GPIO_PIN_RESET : GPIO_PIN_SET); HAL_GPIO_WritePin(FT_D4_PORT, FT_D4_PIN, (CHECK_BIT(data, 4) == 0) ? GPIO_PIN_RESET : GPIO_PIN_SET); HAL_GPIO_WritePin(FT_D5_PORT, FT_D5_PIN, (CHECK_BIT(data, 5) == 0) ? GPIO_PIN_RESET : GPIO_PIN_SET); HAL_GPIO_WritePin(FT_D6_PORT, FT_D6_PIN, (CHECK_BIT(data, 6) == 0) ? GPIO_PIN_RESET : GPIO_PIN_SET); HAL_GPIO_WritePin(FT_D7_PORT, FT_D7_PIN, (CHECK_BIT(data, 7) == 0) ? GPIO_PIN_RESET : GPIO_PIN_SET);__enable_irq();<...>The pins are configured as follow:FT_DX_PORT, FT_DX_PIN, GPIO_MODE_INPUT, GPIO_NOPULL, GPIO_SPEED_HIGHis there anything I can do or example I could follow or inspire myself? (beside implementing some asm?)thanxMart #bitband-bit-bang- Mark as New
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‎2014-11-24 12:31 PM
Is there any rational relationship between the data bits, and the GPIO pins/banks? This is where it helps to think about the design ahead of time, rather than randomly assign available pins.
For multiple contiguous bits you could shift and mask them onto the GPIO(s) ODRUp vote any posts that you find helpful, it shows what's working..
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‎2014-11-24 1:55 PM
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‎2014-11-24 2:00 PM
You might consider going to Bitband addressing for the pins, bypass the libraries, and set/reset the bits directly (but no RMW, not always reliable on I/O pins). For data being serialized do the same thing, convert the data addresses into pointers to large bit arrays with BitBand. It will save you the time on logical operations for particular bits and calculating pointers and bit masks.
Jack Peacock- Mark as New
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‎2014-11-24 2:18 PM
>Is there any rational relationship between the data bits, and the GPIO pins/banks?
not quite sure of you meant here. I am a bit confused. Rational -> D0 = PE0, D1 = PE1, .. D7 = PE7 Irrational -> D0 = PB7, D1 = PA4, D2 = PC3, D3 = PC2, ... Multiple bits can be altered doing an RMW action on GPIOx->ODR, or more swiftly GPIOx->BSRR
Up vote any posts that you find helpful, it shows what's working..
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‎2014-11-24 4:30 PM
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‎2014-11-24 5:38 PM
something like that?:
// GPIOD -> FT_D0_PIN, FT_D1_PIN, FT_D2_PIN, FT_D3_PIN // GPIOE -> FT_D4_PIN, FT_D5_PIN, FT_D6_PIN, FT_D7_PIN GPIOD->ODR = data & 0x0F; GPIOE->ODR = data & 0xF0;- Mark as New
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‎2014-11-24 5:53 PM
GPIOD->ODR = (GPIOD->ODR & 0xFFF0) | (data & 0x0F); // PD0,1,2,3
GPIOE->ODR = (GPIOE->ODR & 0xFF0F) | (data & 0xF0); // PE4,5,6,7 GPIOD->BSSR = (data & 0x0F) | ((~data & 0x0F) << 16); GPIOE->BSSR = (data & 0xF0) | ((~data & 0xF0) << 16);Up vote any posts that you find helpful, it shows what's working..
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‎2014-11-24 6:19 PM
Hi,
I will need some time to digest that. BSRR is split in BSRRL and BSRRH apparently.thnxMart- Mark as New
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‎2014-11-24 6:26 PM
in fact:
#define FT_D0_PORT GPIOD#define FT_D0_PIN GPIO_PIN_14#define FT_D1_PORT GPIOD#define FT_D1_PIN GPIO_PIN_15#define FT_D2_PORT GPIOD#define FT_D2_PIN GPIO_PIN_0#define FT_D3_PORT GPIOD#define FT_D3_PIN GPIO_PIN_1so uhm