Setup: NUCLEO-H503RB with X-NUCLEO-IKS4A1, using STM32CubeIDE.
To familiarize myself with I3C, I am playing around in this setup and have some source code which causes I3C interaction between controller and target. I have a logic analyzer attached, and all looks good.
However, this only works when executing the code without breakpoints. As soon as I break to debug, I can never see the "Tx FIFO not full flag" in the event register but the code relies on it. When I continue stepping, the code obviously misbehaves because it doesn't see the flag either. Code that was executed without breakpoints does see the flag and behaves as expected.
Does the flag auto-clear after a while? Where is this documented? Why do I never see it in the debugger? This prevents me from stepping through the code which contradicts the purpose of my setup.
Example: I hit a breakpoint in the interrupt handler in stm32h5xx_hal_i3c.c.
The event register does not show the TXFNFF:
But the ISR code has obviously seen it because the event register was read in line 1618 (first screenshot above) and stored in it_flags where bit 4 is now set:
Any explanations?
1 ACCEPTED SOLUTION
Accepted Solutions
ST customer support has solved this issue in an internal case (all credit goes to Radek!). The explanation is as follows:
In I3C_EVR, bit 11 (ERRF) is set (as seen in the screenshot above):
Looking at I3C_SER, bit 6 (DOVR) is set (as seen in the screenshot above):
So because of the breakpoint, the Tx FIFO was not filled in time and suffered from an under-run which resulted in the error state where the flag was cleared.
The peripherals are not stopped when the CPU is stopped by the debugger.
ST customer support has solved this issue in an internal case (all credit goes to Radek!). The explanation is as follows:
In I3C_EVR, bit 11 (ERRF) is set (as seen in the screenshot above):
Looking at I3C_SER, bit 6 (DOVR) is set (as seen in the screenshot above):
So because of the breakpoint, the Tx FIFO was not filled in time and suffered from an under-run which resulted in the error state where the flag was cleared.
The peripherals are not stopped when the CPU is stopped by the debugger.
