All,
I am completely stuck with this problem I am facing where I2S receiving data seems to lose its sync with master. I am using STM32F412CG MC.
When I power the MC, it receives data from master device, and plays back nicely. Next time when master stop music, it removes Master clock and when plays music next time, the output is a crap sound. I tried to debug application and found that the RX side input stream is not having bits in the right order which made me believe that this is happening due to Master Slave going out of sync. I looked into data sheet and found that Errata ES0182 23/40
"In slave mode the WS signal level is used only to start the communication. If the I2S(in slave mode is enabled) while the master is already sending the clock and the WS signal level is low, the slave starts communicating data immediately. In this case master and slave will be desynchronized throughout the whole comminication".
WorkAround proposed which says
"I2S peripheral must be enabled when the external master sets the WS line at:
High level when the I2S protocol is seletected".
I have tried this enabling the I2S module after detecting WS high. Actaullly I discard first two highs and than in third high WS, I enable my DMAs and I2S module. But it failed to recover from desync issue. I am using HAL ApIs.
This is how I am trying to stop I2S communication and handle WS detection and start again
HAL_I2S_DMAPause(&hi2s3); // this is modified to disbale I2S module
// Wait untill clocks dies
HAL_Delay(1000);
// Wait for WS Status to pul low
while(WSstatus != GPIO_PIN_RESET);
//Wait for next audio play back after clock removed
while(WSstatus != GPIO_PIN_SET);
//Wait for WSStatus to become low
while(WSstatus != GPIO_PIN_RESET);
//Wait for WSStatus to high again
while(WSstatus != GPIO_PIN_SET);
//Enable DMA and I2S module
HAL_I2S_DMAResume(&hi2s3);
Any help would be highly appreciated. It has become a show stopper for me.
Thanks in advance.
Abi
