I am not able to store the timer counter value from peripheral to memory for every 1s using DMA peripheral interface, please help me

[NPULI.1]

Using STM32F767ZI,

Note:- I have comment some of the statements

[TDK]

This doesn't look like code for an STM32. It looks like it's for a TI chip, if I had to guess.

	DDRD |= (1 << D_RESET) | (1 << D_IN);					//PD3, PD5 output (output to D-ff /RESET and D-in)
	D_FF_PORT |= (1 << D_CLK) | (1 << ICP);					//PD4, PD6 pull up (inputs for resp. T0 en ICP)
 
	DDRB |= (1 << SPI_CLK) | (1 << SPI_DO) | (1 << SPI_CE);	//PB0,1,2 output (to MAX7219)
	DDRB |= (1 << LED);										//PB3 output
	SPI_PORT |= (1 << SPI_CE);								//set CE high
 
 
	TCCR0A = 0;												//normal mode
	TCCR0B |= (1 << CS02) | (1 << CS01) | (1 << CS00);		//clock input extern, RISING edge
	TIMSK |= (1 << TOIE0);									//interrupt bij overflow
 
	TCCR1A = 0;												//normal mode
	TCCR1B |= (1 << CS10);									//prescaler = 1 (10MHz)
	TCCR1B |= (1 << ICES1);									//input capture on RISING edge
	TCCR1C = 0;
	TIMSK |= (1 << TOIE1) | (1 << ICIE1);					//enable interrupt on overflow & input capture
 
...
 
ISR (TIMER0_OVF_vect)										//TIMER0 overflows after 256 counts
{
	input_counter_high++;
}

[Tesla DeLorean]

Not making a particularly strong presentation.

Unrelated main.c, AVR project?

stm32f7xx_hal_msp.c not showing how the ARR is read from the TIM, looks to be using an unrelated DMA resource.

Which source trigger? Which counter is read? Where is it written?

ZIP up a project that's actually compilable.

With this type on endeavour it is important to connect all the dots properly, making random selections is bound to fail.

[NPULI.1]

sorry for above..

Please I have reattached the main.c

My Question remains same:

I am not able to store the timer counter value from peripheral to memory for every 1s using DMA peripheral interface, please help me...

[waclawek.jan]

What's the hardware? What's the trigger source pin? Does that pin work, ie. if you set it as plain GPIO input and observe it in debugger, do you see it changing in IDR as the input level changes? In the "full code", is the relevant CC flag in TIMx_SR set after the trigger occurs?

Where is the memory buffer allocated? Is that memory accessible by DMA? Is that a cached memory? If so, are you aware of cache coherency problems?

If answers to these questions won't help, read out and check/post the TIM, DMA and relevant GPIO registers content, after the attempt to trigger.

JW