How to initialize FDCAN on STM32H753

[tachibana-44]

[Request]
I would like to know the correct procedure for initialization using the INIT bit of the FDCAN's CCCR register.

[Situation]
1) To reset the FIFO status, we are only performing the initialization start using the INIT bit of the FDCAN's CCCR register, and after confirming the end of initialization by reading the same bit, we are setting the RX filter in the Message-RAM (information not changed by INIT) to enable RX-FIFO reception processing. However, despite data that should be acquired by the filter being present on the CAN bus, no RX interrupt is occurring.

2) When checking the FDCAN status using the CAN_MCAN_PSR register in the above situation, the ACT bit in the FDCAN_PSR register remains at 01 (idle) and does not change to 10 (Receiver).

3) When we stop and restart data transmission on the CAN-BUS repeatedly, the ACT bit becomes 10 (Receiver) approximately once every 20 times, and the reception processing begins.

4) When a hardware reset is performed on both the transmitter and receiver sides, the transmission and reception processing operates normally.

5) Based on the situations described in (3) and (4), I suspect that the bit synchronization on the CAN-BUS may have been lost due to the INIT process, preventing reception processing from occurring.

[Question]
* If initialization is performed using the INIT bit in the FDCAN's CCCR register, which registers should be set and how to enable the data flowing through the CAN-BUS to be reacquired? Please provide the correct procedure.

* Additionally, if the usage described above is incorrect, please kindly inform us of the correct method.

Thanks in advance,

Tachibana

[Oleksii]

RM0433
2459
________
This is an example of initialization code for FDCAN for STM32G4 series.. but the principle is the same

void CAN_Config(void) {

	FDCAN_GlobalTypeDef *CAN = FDCAN1;
	uint32_t *filterRAM = (uint32_t*) RAMBaseFDCAN1;
	RCC->APB1ENR1 |= RCC_APB1ENR1_FDCANEN;	// Enable CAN 

	RCC->CCIPR &= ~RCC_CCIPR_FDCANSEL;
	// PLL "Q"   for FDCAN
	RCC->CCIPR |= (0x1 << RCC_CCIPR_FDCANSEL_Pos); //  PLL "Q"
 
	CAN->CCCR |= FDCAN_CCCR_INIT;
	while (!(CAN->CCCR & FDCAN_CCCR_INIT))
		
	CAN->CCCR |= FDCAN_CCCR_CCE; //  Config mode

	/*
	 Baudrate	NSJW	NBRP	NTSEG1	NTSEG2	FDCAN_NBTP (uint32)
	 125000		1		640		543		95		0x21F5F
	 250000		1		320		271		47		0x10F2F
	 500000		2		160		67		12		0x08617
	 800000		1		100		84		14		0x0540E
	 1000000		1		80		67		11		0x0430B
	 */

	// Set the nominal bit timing register
	CAN->NBTP = (1 << FDCAN_NBTP_NSJW_Pos) | (1 << FDCAN_NBTP_NBRP_Pos)
			| (66 << FDCAN_NBTP_NTSEG1_Pos) | (11 << FDCAN_NBTP_NTSEG2_Pos);

	// Clear  RAM

	for (uint8_t i = 0; i < 212; i++) {
		filterRAM[i] = 0;
	};

	/*  FDCAN global filter configuration register (FDCAN_RXGFC)
	 Address offset: 0x0080
	 Reset value: 0x0000 0000
	 */

	CAN->RXGFC = STDfilter_n(2)|EXTfilter_n(0)|ANFS_Reject_rx|ANFE_Reject_rx;

	// ID filters 100 and 80

	filterRAM[0] = STDfilterID_DUAL | STDfilterRxFIFO0
			| STDfilterID1(0x100) | STDfilterID2(0x80); // ID = 100, Standard ID, Store in FIFO0

			

	CAN->IE |= 3; // FDCAN_IE_RF0NE_| RF0FE
	CAN->ILS |= 1;  // RXFIFO0: RX FIFO bit grouping the following interruption
	CAN->ILE |= 2;  // Enable IT0

	//FDCAN1->IE |= FDCAN_IE_RF0NE;

	// Normal mode
	CAN->CCCR &= ~FDCAN_CCCR_INIT; // exit init
	while (CAN->CCCR & FDCAN_CCCR_INIT)
		;
	NVIC_EnableIRQ(FDCAN1_IT1_IRQn);

}

But your memory size is different.