[Request]
I would like to know the correct procedure for initialization using the INIT bit of the FDCAN's CCCR register.
[Situation]
1) To reset the FIFO status, we are only performing the initialization start using the INIT bit of the FDCAN's CCCR register, and after confirming the end of initialization by reading the same bit, we are setting the RX filter in the Message-RAM (information not changed by INIT) to enable RX-FIFO reception processing. However, despite data that should be acquired by the filter being present on the CAN bus, no RX interrupt is occurring.
2) When checking the FDCAN status using the CAN_MCAN_PSR register in the above situation, the ACT bit in the FDCAN_PSR register remains at 01 (idle) and does not change to 10 (Receiver).
3) When we stop and restart data transmission on the CAN-BUS repeatedly, the ACT bit becomes 10 (Receiver) approximately once every 20 times, and the reception processing begins.
4) When a hardware reset is performed on both the transmitter and receiver sides, the transmission and reception processing operates normally.
5) Based on the situations described in (3) and (4), I suspect that the bit synchronization on the CAN-BUS may have been lost due to the INIT process, preventing reception processing from occurring.
[Question]
* If initialization is performed using the INIT bit in the FDCAN's CCCR register, which registers should be set and how to enable the data flowing through the CAN-BUS to be reacquired? Please provide the correct procedure.
* Additionally, if the usage described above is incorrect, please kindly inform us of the correct method.
Thanks in advance,
Tachibana
