I am using the DMA SPI as slave on a stm32-F401. I use:
DMA SPI SlaveHAL_SPI_TransmitReceive_DMA(&hspi2, pTxData, pRxData, len};
When I do this a len amount of zeros is written to the FIFO Tx. For my use case I need to write to the Tx buffer using serial communication. I can successfully write to the Tx buffer using serial but when I try to retrieve this data using a SPI master, the initial zeros are first in line.
Is it necessary to write on the FIFO Tx when initializing DMA SPI? Is there a way to avoid this? If this is the expected behavior, how to FLUSH the FIFO Tx to avoid reading this unwanted data?
I found 2 answers on how to flush the FIFO Tx but they are too vague for my little knowledge. A solution from https://community.st.com/s/question/0D50X00009XkeT8/stm32f0-spi-txfifo-flush sugests:
- Reset SPI in RCC
- complete init SPI
And another one from https://community.st.com/s/question/0D50X00009XkhXo/dma-fifo-flush-issue says:
- manually loading the first word from into the DR of the SPI channel
- configuring the DMA channel to start at the next word in my buffer (obviously reducing the length by 1 word)
Are these the way to go? If so, I could some more explanation on how to go about with the implementation.
