2025-04-16 8:09 PM
Hello every
I want to increase STM32G473 FDCAN Tx buffer and Rx buffer size,
In STM32G473 datasheet >> "A 3-Kbyte message RAM memory implements filters, receive FIFOs, receive buffers, transmit event FIFOs, transmit buffers. This message RAM is shared between the threeFDCAN modules."
In my project, I used three FDCAN(FDCAN1 FDCAN2 FDCAN3),However, after testing, if there is no delay, each FDCAN can only send a maximum of 3 data.This seems to match the SRAMCAN_TFQ_NBR parameter.But when I modified this parameter, the data sent became very strange, and the CAN analyzer could not receive normal data.
Does anyone know how to increase the tx buffer size of FDcan? Besides this, I would also like to know how to increase the size of the rx buffer
If you have any questions, please feel free to discuss with us,Thanks!
Solved! Go to Solution.
2025-04-21 8:23 AM - edited 2025-04-22 4:07 AM
Hello,
I don't think you are allowed to modify the parameters in the driver (stm32g4xx_hal_fdcan.c).
Meanwhile please refer to the AN5348 "Introduction to FDCAN peripherals for STM32 MCUs" / section: 4.2 RAM management.
2025-04-21 8:23 AM - edited 2025-04-22 4:07 AM
Hello,
I don't think you are allowed to modify the parameters in the driver (stm32g4xx_hal_fdcan.c).
Meanwhile please refer to the AN5348 "Introduction to FDCAN peripherals for STM32 MCUs" / section: 4.2 RAM management.
2025-04-21 11:09 PM
Hello, mEAllenm
Thanks for your advice, I'll check out the manual again, keep in touch.
2025-11-10 5:31 AM - edited 2025-11-10 5:32 AM
As far as I know, on the STM32G473 the message RAM cannot be allocated freely, and the FIFO size is fixed at 3 messages.
The reference manual RM0440 explains this clearly.
In AN5348, the table Applicable products lists the STM32G4 series, but I believe this is a mistake.
2025-11-10 6:35 PM
Hello, ivanobono,
Based on my testing, I think you are right bro. When I modify TX FIFO size, FDCAN cannot not work, It must be 3.
Thinks for you replay
2025-11-11 2:47 AM
You can get an interrupt with each receive event and transfer with low priority to your own larger buffer.
2025-11-11 2:55 AM
via software everything is feasible; the discussion concerns only the hardware buffer and the AN5348, which provides instructions that are not applicable to this CPU
2025-11-11 3:12 AM
Hello Uwe,
I did indeed use software methods to solve the multi-frame transmission blocking problem.
anyway, Thanks for your reply.