cancel
Showing results for 
Search instead for 
Did you mean: 

How to generate multiple pulses of different lengths with a STM32 Timer

AAnge.3
Associate

Is there a way to generate multiple pulses of different lengths with a timer?

This is needed to perform a double pulse test, by controlling the B6-Bridge Driver of a B6-Bridge.

The first pulse is longer than the second pulse (e.g 300 us). The second pulse is shorter (20 us) and comes after a short pause after the first pulse stopped (10 us).

LOW -> First pulse (HIGH for 300 us) -> pause (LOW 10 us) -> second pulse (HIGH for 20 us) -> LOW

As the time periods of these pulses can get pretty short, I was adviced to realise this task with the PWM-generation via timer on the STM32F407 Discovery Board (up to 168MHz).

In the end I need to have six outputs for these PWMs Two of them are used for the pulses, while the rest is always LOW. According to which phase of the motor is currently tested, I'll need to change which of the six outputs is pulsed and which are not. One of the two pulsed outputs is like I already stated above, the othere output is to be the inverted version of the pulses with a deadtime.

Pulse lenghts and deadtime should be configurable by the user.

I'd be very pleased if someone could help me on this topic.

2 REPLIES 2

STM32 TIM are good at modulating pulse widths where the frequency is the same.

For complex widths you can DMA widths into the CCRx register at TIM Update

For complex pin patterns on multiple channels/pins you might do better committing a GPIO Bank and driving a pattern buffer at a defined rate with TIM+DMA into GPIOx->BSRR

Tips, buy me a coffee, or three.. PayPal Venmo Up vote any posts that you find helpful, it shows what's working..

Set ARR and CCRx for the first pulse, then set the preload bits for ARR and CCRx and set into them the second pulse's values. Enable Update interrupt, and in the ISR write zeros to ARR and CCRx. ISR latency should be below 300us but that should be fairly easy to ensure on an 'F4. Then just enable counter.

A more sturdy approach is to use DMA and load both ARR and CCRx using the DMAR/DCR mechanism.

Using TIM1 and TIM8, you have output pairs available with deadtime. Read the TIM chapter in RM.

JW