How to Configura TIM1CLK TIMXCLK

[esiqueira]

Posted on July 10, 2012 at 16:09

According to the attached. I do not understand how to set the clock correctly TIMER From what I understand, TIMXCLK PCLK1 = 2 * and 2 * = TIM1CLK PCLK2 But not found in the manual or the information in the datasheet. Can anyone help me?

void vConfigura_RCC(void)

{  RCC_DeInit();             // Deinitialize RCC  RCC_HSEConfig(RCC_HSE_ON);           // Enable HSE (external crystal)  HSEStartUpStatus = RCC_WaitForHSEStartUp();       // Wait till HSE is ready    if (HSEStartUpStatus == SUCCESS)  {     FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable);   // Enable Prefetch Buffer   FLASH_SetLatency(FLASH_Latency_2);       // Flash 2 wait state   RCC_HCLKConfig(RCC_SYSCLK_Div1);       // HCLK = SYSCLK  = 72Mhz   RCC_ADCCLKConfig(RCC_PCLK2_Div6);        // ADCCLK = PCLK2/6 = 12MHz   RCC_PCLK2Config(RCC_HCLK_Div1);        // PCLK2 = HCLK  = 72Mhz   RCC_PCLK1Config(RCC_HCLK_Div2);        // PCLK1 = HCLK / 2 = 36Mhz   RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_9);  // PLLCLK = 8Mhz x 9 = 72Mhz   RCC_PLLCmd(ENABLE);           // Enable PLL      while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET);  // Wait till PLL is ready     RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);      // Select PLL as system clock source                     while (RCC_GetSYSCLKSource() != 0x08);      // Wait till PLL is used as system clock source  }

  /* PCLK1 = HCLK/4 */

  RCC_PCLK1Config(RCC_HCLK_Div8);   // Ajusta CLOCK dos Perifericos de APB1   RCC_PCLK2Config(RCC_HCLK_Div8);   // Ajusta CLOCK dos Perifericos de APB2     /* TIM3 clock enable */   RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM4, ENABLE);   RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1, ENABLE);     /* GPIOA and GPIOC clock enable */   RCC_APB2PeriphClockCmd(  RCC_APB2Periph_GPIOB |               RCC_APB2Periph_GPIOA |                            RCC_APB2Periph_AFIO, ENABLE); } #timer-clock-rcc

[Tesla DeLorean]

Posted on July 10, 2012 at 16:26

You need to look at the RCC Clock Tree in the REFERENCE MANUAL, See Pg 123 ''Figure 11 Clock Tree''

http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/REFERENCE_MANUAL/CD00171190.pdf

The timers here both look to be clocked at 18 MHz.

[esiqueira]

Posted on July 10, 2012 at 16:57

THANKS Clive1

If prescaler not set=1, then prescaler=2;

[Tesla DeLorean]

Posted on July 10, 2012 at 17:17

It's really to let the timers run at 72 MHz (logic rated at this speed) when the bus is at 36 MHz, but you can't exceed the input clock. Basically you lose a divider, rather than have a multiplier.

Where HCLK = 72 MHz RCC_HCLK_Div1, TIMCLK 72 MHz RCC_HCLK_Div2, TIMCLK 72 MHz RCC_HCLK_Div4, TIMCLK 36 MHz RCC_HCLK_Div8, TIMCLK 18 MHz The part always generates the slower clocks in the divider chain, the prescaler just picks which one to gate out (tap) to down stream logic.

[esiqueira]

Posted on July 10, 2012 at 18:38

Let me see if I understood...

Here the HCLK was configured with the same frequency of the SYSCLK=72MHz

RCC_HCLKConfig(RCC_SYSCLK_Div1);       

// HCLK = SYSCLK  = 72Mhz

Here, The Clock of APB1 and APB2 was configures of  HCLK/4=18MHz

RCC_PCLK1Config(RCC_HCLK_Div4);  

// Ajusta CLOCK dos Perifericos de APB1

RCC_PCLK2Config(RCC_HCLK_Div4);  

// Ajusta CLOCK dos Perifericos de APB2

I can Configure with RCC_HCLK_Div1, Div2, Div3 or Div4 like you show on table

In this case the TIM1CLK and TIMXCLK =36MHz, because:

TIMXCLK=RCC_PCLK1Config*2;

TIM1CLK=RCC_PCLK2Config*2;

on the page 123 (REFERENCE_MANUAL)

Only if the RCC_PCLK(X)Config=1

TIMXCLK=RCC_PCLK1Config*1;

TIM1CLK=RCC_PCLK2Config*1;

on the page 123 (REFERENCE_MANUAL)

THANKS again Clive1