how to check DMA ISR source within a channel

[denis]

Posted on October 18, 2013 at 10:21

Say on my device, in DMA ch1  i can have 3 periphs, plus possibly mem2mem.

If I installed an isr how do I check from which periph (or mem) it came from, by reading  DMA_CPARx PA bits ?  #dma

[Tesla DeLorean]

Posted on October 18, 2013 at 13:51

I'm not keeping track of what STM32 part you're using, the meaning of Channel and Stream has a different means depending on the context.

On the F1 series each Channel has it's own IRQ Handler, and own TCx and HTx bitsOn the F2/F4 series the Channel is a mux-able source, not something you can uniquely identify in a status register, each Stream (functional DMA unit) can select One channel as a peripheral source. Each Stream has it's own IRQ, and TCx / HTx bits.

[denis]

Posted on October 18, 2013 at 14:15

my device is  STM32L15xx,

DMA1 Channel1 can be used by ADC1, TIM2_CH2, TIM2_CH1 peripherals. You can have isr _per_channel_, thus as far as I understood it,  same isr for 3 cases. Thus within channel/isr, which periph caused it

[Tesla DeLorean]

Posted on October 18, 2013 at 15:46

Maybe you're looking at a different document (RM0038 Rev2) but DMA1 Channel1 can service either ADC1, TIM2_CH3 or TIM4_CH1

It can use multiple sources, and thus can't identify them, you get to pick one source from each column (Table 33 Summary of DMA requests for each channel) The exact combination of peripherals or TIMx_CHx triggers will depend on which you need. One combination that full utilizes DMA1 would be ADC1, USART3_TX, USART3_RX, USART1_TX, USART1_RX, USART2_RX, and USART2_TX . Bingo! your card is full. Other combinations are possible, but constrained by the chart.

[denis]

Posted on October 18, 2013 at 16:32

RM0038, REV 8

>..but DMA1 Channel1 can service either ADC1, TIM2_CH3 or TIM4_CH1 Is this different to what I wrote? Thus If I have dma_ch1 isr called, and want to know from which periph the transfer was complete now, what do I check?  I thought  (as above) from periph src register ...

[Tesla DeLorean]

Posted on October 18, 2013 at 16:53

>..but DMA1 Channel1 can service either ADC1, TIM2_CH3 or TIM4_CH1

Is this different to what I wrote? - ADC1, TIM2_CH2, TIM2_CH1

Clearly it is, and I'm dyslexic, but you still seem to be talking about the wrong TIM/CH combinations.Thus If I have dma_ch1 isr called, and want to know from which periph the transfer was complete now, what do I check?  I thought  (as above) from periph src register ... But you don't have that choice, you'd configure ADC1 to be generating the DMA request, and DMA1_Channel1 to accept that request, what TIM2_CH3 and TIM4_CH1 are up to is irrelevant. I haven't delved into the silicon implementation enough to know if you could set them up in a conflicting manner, ST shows an OR gate, but it wouldn't be a recommended approach. The DMA is serviced by HW, you'd get a transfer per request, this wouldn't even show up in status bits. It's not generating an IRQ per individual transfer, unless you configure the length as such, which would tend to mitigate the utility of DMA vs servicing the peripheral directly.

[jpeacock2399]

Posted on October 19, 2013 at 01:03

The STM32F1 DMA unit won't tell you which peripheral is enabled for DMA.  However you can look at the DMA peripheral address register and deduce the source based on which peripheral uses that register address.

On F2 and later there is a field in the DMA configuration register which tells you what source is enabled.   Jack Peacock

[Tesla DeLorean]

Posted on October 19, 2013 at 01:14

Hopefully you can figure it out without checking the DMA by actually arbitrating use of the resource at a driver level.

[denis]

Posted on October 21, 2013 at 10:19

yep, that will do