How to achieve exact SCL clock timings for I2C master in transmit mode?

[Georgy Moshkin]

According to RM, "The I2C detects its own SCL low level after a tSYNC1 delay depending on the SCL falling edge", and

i2sT=1/i2sclk

tSCL=tSYNC1+tSYNC2+((SCLH+1)+(SCLL+1))*(PRESC+1)*i2sT

fSCL=1/tSCL

I tried different PLL clock configurations and altered automatically generated STM32Cube values in I2C_TIMINGR register, but was not able to achieve exact values. For example, 100kHz STM32Cube settings resulted in actual SCL value around 96kHz.

Also description states that "I2C detects its own SCL low level", does it mean that SCL clock may differ from board to board depending on I2C pullup resistor tolerances? I've tried to use I2C_NOSTRETCH_ENABLE, but it does not have effect on this issue. Maybe generate SCL clock with exact timings, for example using PWM on SCL line and using transmitter in slave mode and emulate master mode? Or emulate additional slave on the line and use it to stretch slightly higher clock of 101kHz down to 100kHz? For my application driving external DAC over I2C interface require more precise timing.

[TDK]

> For my application driving external DAC over I2C interface require more precise timing.

What DAC can't cope with 96 kHz on I2C?

Please always include your chip number in the post.

[Georgy Moshkin]

for example dac7571, mcp4725. Continous write operation, maximum I2C bitrate is around 3MHz, settling time is 10us and 6us.

But my focus is not on how fast DAC is, but on precise timings of I2C SCL clock. Can we run I2C SCL at 100kHz, then compare it to 100kHz PWM output from same microcntroller on the scope and see no drift over time. Currently I think that one possible solution would be using timer ocr/ccr in circular DMA mode with I2C data transmit register address.

[Piranha]

Do you need those frequencies to be exactly 100 kHz or do you need them to be exactly equal? Even if you cannot get an exact 100 kHz from I2C module, you definitely can find some close frequency to which you can exactly adjust the TIM peripheral.

[Georgy Moshkin]

From my current understanding, capacitance variation on SCL pin may induce changes in t_SYNC1 and t_SYNC2 timings. I2C module can work at any integer multiple / division of STM32 internal ADC/DAC frequency, just need integer-ratio sync between all existing peripherals.