How is the STM32 required data hold time during read from QuadSPI flash guaranteed in the Discovery kit STM32L496G-DISCO?

[S.Nygaard]

We use STM32L496QGI6 with a 512Mb external flash connected to a QuadSPI interface.

Principally like the Discovery kit STM32L496G-DISCO (with STM32L496AG MCU and 64Mb flash).

We wonder how the STM32 required data hold time during read from flash can be guaranteed.

Looking at STM32L496xx product datasheet Table 98 (QUADSPI characteristics in DDR mode), the required Data input hold time is minimum 6.5ns.

(In SDR mode/Voltage Range 1 in Table 97 it is minimum 4ns).

The used flash on the Discovery kit (MX25R6435FM2IL0, which is principally the same as we use) provides according to the flash IC datasheet an output hold time tCLQV of minimum 0ns (Table 17 AC Characteristics). Looking across flash devices, 1ns seems to be a typical value.

How can the required hold time be guaranteed in such setup? Can some timings be adjusted?

[ChahinezC]

Hello @S.Nygaard​,

The data input setup time and data output setup time are part of the values characterizing the QuadSPI interface, and guaranteed by characterization results which means that these values can not be changed by user configuration.

To verify whether a memory is compatible with the STM32 QuadSPI interface in our devices, it is mandatory to check the memory datasheet and make sure the values of the input/output hold time are on the same page with our provided values.

Another thing is to ensure that you are comparing the values correctly; for example the input hold time on the MCU's side to the output hold time on the memory's side and vice versa.

I hope my answer has helped you, when your question is answered please close this topic by marking as Best the reply that answered you, it will help other find that answer faster.

Regards,

Chahinez.

[S.Nygaard]

Thank you for the response, but unfortunately, it do not answer the question.

As we realized that the Discovery kit uses the same QuadSPI setup as we do, we better use the Discovery kit as reference for the question. If we can be convinced that the Discovery QuadSPI setup is properly configured, then we also afterwards can get our own setup in proper shape.

So, with the ST Discovery kit STM32L496G-DISCO as reference, we find the following characterizations in datasheets regarding hold times when data is flowing from the flash (data output) towards the MCU (data input):

Provided hold time from the Flash Macronix MX25R6435FM2IL0 data output:

Minimum 0ns (no hold time is guaranteed)

Source: https://www.macronix.com/Lists/Datasheet/Attachments/8868/MX25R6435F,%20Wide%20Range,%2064Mb,%20v1.6.pdf

Table 17 "tCLQX"

Required hold time for the MCU STM32L496AG data input:

Minimum 6.5ns.

Source: https://www.st.com/en/microcontrollers-microprocessors/stm32l496ag.html

Table 98 "thf(IN)" and "thr(IN)

The required hold time for the MCU data input seems not to be guaranteed by the flash data output hold time.

Is this right understood or do we miss something?