How does the Right bit shift in oversampling ADC works; Can I increase my ENOB without shifting bits?

[JBazm.1]

So, I'm trying to increase my ENOB from 13.7 bits to 16 bits or higher through the hardware Oversampling system, if possible:

MCU: STM32H750V

1) If I increase the Oversampler ratio to 128 or 256 without any bit shift, do I get the increased ENOB?

2) My application does not need the absolute accuracy, only precision(or resolution), and low noise. How can I increase the ADC bits to 17 or 18 bits, and receive 18-bit data in my memory buffer?

I use 16-bit DMA transfers into a 16-bit Memory buffer, and everything works. Then, as soon as I change the DMA and buffer size to 32 bits to receive higher bits, I get very large and wrong values, what would be the culprit?

I'm out of the Application Notes and Reference Manual to read, and I couldn't see a clear explanation of how to do bit shifting or achieve higher than 16-bit resolutions..

And the Fact that I'm a bit of a noob doesn't have to do anything with it of course.

Any help would be appreciated.

[TDK]

If it's a steady signal, you can increase ENOB in this way, yes.

However, the readings you get from a DC signal do not have a normal distribution so you will run into numerical artifacts that prevent you from getting more than a few extra bits, certainly before you hit 16 bits of "precision".

Do the oversampling in software and you will see this effect.

[JBazm.1]

I'm not sure what you mean by "steady signal"; the signal of interest is an exponential ramp with some good few tens of LSB of white noise on it. The absolute maximum frequency component I'll be looking for would be less than 10KHz, and the most important components are all under 2KHz.

I have already succeeded with the oversampling ratio of 128 and 7 right bit-shift, which gives me a very good, low-noise, precise measurement.

Now the question is, how do I get more than 16 bits of resolution? I just need to see the relative changes in my LSB values.

The Idea is to use ADC1 and ADC2 in dual-interleaved mode to get the highest oversampling ratio yet still be within the required sample time (100us or less).

[AScha.3 · Accepted solution]

>Now the question is, how do I get more than 16 bits of resolution?

So use oversampling , but no right shift. Then you get all bits...16+7 = 23 b here.

And read full data register, 32b.

[JBazm.1]

Thank you very much, it worked this time, although I have tried every combination of bit-shifting and buffer sizes and whatnot before, but it would not give valid results, and now I have found out why.

It was the Clock source!

For some reason, at the beginning of development, I ended up using the PLL3R for my ADC clock source instead of PLL2P, and apparently, that was the culprit for invalid reads.

While using PLL3R clock source values above 25Mhz of ADC clock would create wrong results, by shifting to PLL2P I can use 50Mhz for ADC clock with great results.(I'm aware of the fact that in the LQFP100 package, using ADC clock above 18 to 19MHz will have missing codes in 16-bit mode, I'm just experimenting.)

But thank you.