how can i deal with 105's clock?

wuhaibin011 · ‎2011-02-06

Posted on February 07, 2011 at 08:01

js23 · ‎2011-05-17

Posted on May 17, 2011 at 14:24

When USB is used, PLLCLK must be 48MHz or 72Mhz. PLLCLK is the source for SYSCLK and this is again the source for APB2.

This means: APB2 can only be 48MHz or 72MHz, too (or fractionals of these frequencies). 64MHz will not be possible.

wuhaibin011 · ‎2011-05-17

Posted on May 17, 2011 at 14:24

Thank you for your answer.

i have to find to another way to finish the project.

and from your answer ,i can also get a message: when i use the USB ,the ADC

can't be setted to 56M, so the ADC will not get the fasted speed.

is it right?

js23 · ‎2011-05-17

Posted on May 17, 2011 at 14:24

Yep. When SYSCLK is 72MHz, fastest ADC speed is 12MHz. This means max. 857 kSamples/s (= 1.17µs conversion time).