High speed peripheral (timer) and low speed core clock, possible?

[klauskvik]

Posted on September 11, 2012 at 22:33

Hi

I would like to run a STM32L151 (M3) with low core clock (to reduce current comsumption) and with high peripheral speed (say 16MHz PWM clock). A possible solution (HSI internal clock for ADC is routed to the MCO (main clock output) and fed back into the timer block:

http://www.electronicsdesign.dk/tmp/STM32L151_Clock_RoutingExample_Sm.pdf

1.

Setup SYSCLK for 2MHz

2.

Run HSI via MCOSEL to MCO (16MHz clock out)

3.

Route MCO to ETR

4.

Route ETR to CK_PSC via TIMx_SMCR setting (now we have 16MHz for the timer clock)

A problem might be according to figure 104 CK_INT is used to syncronize the count up/down and then the resulting clock to the timer cannot be faster than the core clock even if the ETR input has higher frequency. However, maybe TI1FP1 can be used and will not be affected by CK_INT. So, the question, can the core clock be run lower than the peripheral clock usiing this method or is there another way to acchieve this goal? Regards Klaus #core-peripheral-clock

[klauskvik]

Posted on September 11, 2012 at 22:36

Snip...

Please note this is actually a link to a PDF: (if that was not clear)

http://www.electronicsdesign.dk/tmp/STM32L151_Clock_RoutingExample_Sm.pdf

[Tesla DeLorean]

Posted on September 11, 2012 at 23:45

As I recall all the inputs are resynchronized against the peripheral clock (APB/AHB), or crossing clock domains. I don't believe any of this is tolerant to inverted clock slope you propose. ie downstream clocks need to be the same, or slower, and synchronous to each other.

Timer inputs are prone to nyquist sampling issues like aliasing. Something a number of forum members has definitely encountered. Suggest you look at something like WFI to halt the core when no work is pending.