High-Speed Data Logging Architecture: 10MSPS Interleaved ADC to eMMC + USB on STM32H743

[Krawyn]

Hello,

I am designing a high-speed data logging architecture using STM32H743VIHx. I would like the community to validate my DMA architecture and answer specific questions about eMMC access. I did not find answers in the forum and I am also not an expert in microcontroller hardware/software architecture.

--- SYSTEM OVERVIEW ---

The logging produces a continuous signal sampled by the ADC. I need to log raw data samples along with GPS and IMU data to an eMMC for post-processing.

Key parameters:
- ADC: 14-bit dual interleaved on PA6 (ADC12_INP3), differential ~10 MSPS effective
- eMMC: S32 GB, eMMC 5.1
- SDMMC1 in 8-bit MMC mode
- IMU: on SPI2 (PB12-15) at 8 kHz
- GPS: on UART4 at 115200 baud

--- PROPOSED DMA ARCHITECTURE ---

Four concurrent DMA paths:

1. ADC1+ADC2 interleaved → DMA1_Stream0 → AXI SRAM (ping buffer)
Triggered by ADC1 EOC, reads CDR register (32-bit = 2 interleaved samples)
Rate: ~20 MB/s
Priority: VERY HIGH

2. AXI SRAM (pong buffer) → MDMA_Channel0 → SDMMC1 → eMMC
Triggered after 128 consecutive measurements
Burst write: 2.56 MB per transfer
Rate: ~45 MB/s burst
Priority: HIGH

3. SPI2 → DMA1_Stream4 → AXI SRAM (IMU buffer)
Triggered by IMU INT1 at 8 kHz
Rate: ~1 MB/s
Priority: MEDIUM

4. UART4 → DMA2_Stream2 → AXI SRAM (GPS buffer)
Circular DMA, UART idle detection
Rate: ~14 KB/s
Priority: LOW

Ping-pong buffers in AXI SRAM, 32-byte aligned, DCache cleaned before MDMA read.

--- QUESTIONS ---

Q1 - ADC dual interleaved validation
Is PA6 (ADC12_INP3) a valid fast channel for dual interleaved differential mode at 10 MSPS / 14-bit on the STM32H743VIHx ? AN5354 states 10 MSPS at 14-bit is achievable on fast channels but does not list specific pins for the 100-pin package. I have seen a community post confirming ADC12_INP3 (PA6), ADC12_INP4 (PC4), and ADC12_INP5 (PB1) as the only fast channels.

Q2 — DMA parallelism
Can DMA1_Stream0 (ADC→SRAM) and MDMA_Channel0 (SRAM→SDMMC) run simultaneously without stalling the ADC path? My AXI SRAM load calculation gives ~66 MB/s total against ~960 MB/s realistic bandwidth — well within limits. However I am concerned about bus arbitration causing microsecond stalls on the ADC DMA during MDMA burst writes. Has anyone experienced ADC sample loss during simultaneous MDMA eMMC writes?

Q3 — eMMC offline readout via USB
After the flight I need to read the raw eMMC data on a PC for post-processing.
Can I implement USB MSC using the H743 USB OTG FS on PA11/PA12. The STM32 reads eMMC via SDMMC1 and exposes it as a USB drive. Is it possible ? What component do I need to add ?

Q4 — eMMC raw sector access without filesystem
I am writing raw sectors directly (no FatFS) using HAL_MMC_WriteBlocks_DMA for performance. After plugging via USB MSC, will the PC see the device as a raw disk ? Or does USB MSC require the device to have a valid MBR/partition table?

Thank you for any feedback. I am really not an expert in this domain and I tried my best to gather informations. But I am not 100% sure of what I found as it is a mix of forums answers, datasheets and Claude AI help.

Florian

[Ozone]

First, I don't have experience with the H7 series as such.

> AN5354 states 10 MSPS at 14-bit is achievable on fast channels but does not list specific pins for the 100-pin package.

This information is found in the datasheet, especially the pinout section with GPIO AF options. I have seen such "fast channel" comments as table footnotes.

> Can DMA1_Stream0 (ADC→SRAM) and MDMA_Channel0 (SRAM→SDMMC) run simultaneously without stalling the ADC path?

Things get a bit more complex here.
Check the reference manual sections describing the bus matrix, and the corresponding sections for the involved peripherals. DMA transfers and core data memory accesses can indeed interfer with each other if they use the same bus.

> The STM32 reads eMMC via SDMMC1 and exposes it as a USB drive. Is it possible ? What component do I need to add ?

Definitely possible.
You could check for an USB MSC example for your MCU, build and test it, and integrate it into your application.

> I am writing raw sectors directly (no FatFS) using HAL_MMC_WriteBlocks_DMA for performance. After plugging via USB MSC, will the PC see the device as a raw disk ? Or does USB MSC require the device to have a valid MBR/partition table?

Not sure what you mean.
If you speak about using the H7 as USB-MSC device, the internal organisation of the eMMC memory does not really matter in this case.
But you need to present it to the host system (the PC) as a file system it understands - e.g. FAT32.

[FBL]

Hi  @Krawyn 

1. I assume already answered here as well.
2. Even if your AXI SRAM bandwidth calculation is well within limits, bus arbitration can introduce µs stalls. These stalls, especially during MDMA burst writes, can cause ADC sample loss or overruns in similar scenarios. This is due to the way STM32 bus matrices handle multiple masters competing for the same memory resources. Arbitration delays can occur, particularly if both DMA and MDMA target the same SRAM region at the same time. To minimize this risk, use staged transfers, synchronize operations with callbacks, assign higher priority to ADC DMA if needed, and balance memory accesses. 
3. Check this example application article for implementing a standalone USB Mass Storage device on STM32 with eMMC. It could be useful in your case.
4. Regarding USB MSC device, USB Mass Storage Class exposes a block device, so a PC can access sectors directly. However, for the PC to automatically mount and use the storage as a normal disk, a valid partition table and usually a valid filesystem are expected. So,

• Raw sector access is possible
• USB MSC device does not inherently require a filesystem
• But without a valid MBR/GPT and filesystem, the PC may detect the media as a raw/unformatted disk rather than a usable volume.