Hello ST Community,
I am currently evaluating an architecture based on STM32H7 series MCUs (STM32H743 / STM32H7A3) and would appreciate guidance on external memory scalability and best practices.
Target Architecture
- Bootloader in internal Flash
- Main application stored and executed from external OctoSPI NOR Flash (XIP mode, memory-mapped at 0x90000000)
- External RAM for buffering (TCP/IP, DLMS stack, application data)
Planned External Memory
- External NOR Flash via OctoSPI (large size, potentially >512 Mbit)
- External RAM target: ~256 MB (initial requirement)
Key Questions
1. XIP Execution from OctoSPI NOR
- Is full application execution from OctoSPI NOR considered reliable for production systems?
- What are the recommended:
- MPU settings for external flash (cacheable, bufferable, execution attributes)?
- I-Cache / D-Cache configuration?
- Are there known limitations regarding branch-heavy code or interrupt latency when executing from external flash?
2. External SDRAM via FMC
- What is the maximum supported SDRAM size per FMC bank on STM32H7?
- Is there any practical way to interface >64 MB SDRAM, or is this limited by FMC addressing (row/column/bank constraints)?
- Any validated configurations beyond 32 MB?
3. Large External RAM Requirement (~256 MB)
- Given the above constraints, is there any recommended approach within STM32H7 to reach ~256 MB external RAM?
- Or should this requirement be considered outside the practical limits of the platform?
4. Alternative RAM Options
- Experience with HyperRAM / PSRAM via OctoSPI:
- Maximum supported size?
- Stability and bandwidth compared to SDRAM?
- Can multiple external RAM devices be combined effectively?
5. Performance & Cache Coherency
- Best practices for using external SDRAM with:
- TCP/IP stack buffers
- DMA-based peripherals (ETH, etc.)
- Recommended approach for handling D-Cache coherency:
- MPU non-cacheable regions vs manual cache maintenance?
6. Code & Data Placement Strategy
- Recommended partitioning between:
- Internal Flash vs external XIP
- Internal RAM vs external SDRAM
- Should all interrupt handlers and time-critical code be strictly placed in internal memory?
7. External Flash Scaling
- Practical limits for OctoSPI NOR in memory-mapped mode:
- Maximum usable size for XIP?
- Any constraints beyond 1 Gbit devices?
8. Reference Designs
- Any ST reference designs or application notes demonstrating:
- OctoSPI XIP + FMC SDRAM combined usage
- High-memory STM32H7 applications
Objective
To determine whether STM32H7 can support this architecture or if the memory requirements (especially ~256 MB RAM) require moving to a different platform.
Appreciate any insights, especially from those with production experience on STM32H7 external memory systems.
Best Regards,
KamalDev
