Hello,
I am designing a high-speed data logging architecture using STM32H743VIHx. I would like the community to validate my DMA architecture and answer specific questions about eMMC access. I did not find answers in the forum and I am also not an expert in microcontroller hardware/software architecture.
--- SYSTEM OVERVIEW ---
The logging produces a continuous signal sampled by the ADC. I need to log raw data samples along with GPS and IMU data to an eMMC for post-processing.
Key parameters:
- ADC: 14-bit dual interleaved on PA6 (ADC12_INP3), differential ~10 MSPS effective
- eMMC: S32 GB, eMMC 5.1
- SDMMC1 in 8-bit MMC mode
- IMU: on SPI2 (PB12-15) at 8 kHz
- GPS: on UART4 at 115200 baud
--- PROPOSED DMA ARCHITECTURE ---
Four concurrent DMA paths:
1. ADC1+ADC2 interleaved → DMA1_Stream0 → AXI SRAM (ping buffer)
Triggered by ADC1 EOC, reads CDR register (32-bit = 2 interleaved samples)
Rate: ~20 MB/s
Priority: VERY HIGH
2. AXI SRAM (pong buffer) → MDMA_Channel0 → SDMMC1 → eMMC
Triggered after 128 consecutive measurements
Burst write: 2.56 MB per transfer
Rate: ~45 MB/s burst
Priority: HIGH
3. SPI2 → DMA1_Stream4 → AXI SRAM (IMU buffer)
Triggered by IMU INT1 at 8 kHz
Rate: ~1 MB/s
Priority: MEDIUM
4. UART4 → DMA2_Stream2 → AXI SRAM (GPS buffer)
Circular DMA, UART idle detection
Rate: ~14 KB/s
Priority: LOW
Ping-pong buffers in AXI SRAM, 32-byte aligned, DCache cleaned before MDMA read.
--- QUESTIONS ---
Q1 - ADC dual interleaved validation
Is PA6 (ADC12_INP3) a valid fast channel for dual interleaved differential mode at 10 MSPS / 14-bit on the STM32H743VIHx ? AN5354 states 10 MSPS at 14-bit is achievable on fast channels but does not list specific pins for the 100-pin package. I have seen a community post confirming ADC12_INP3 (PA6), ADC12_INP4 (PC4), and ADC12_INP5 (PB1) as the only fast channels.
Q2 — DMA parallelism
Can DMA1_Stream0 (ADC→SRAM) and MDMA_Channel0 (SRAM→SDMMC) run simultaneously without stalling the ADC path? My AXI SRAM load calculation gives ~66 MB/s total against ~960 MB/s realistic bandwidth — well within limits. However I am concerned about bus arbitration causing microsecond stalls on the ADC DMA during MDMA burst writes. Has anyone experienced ADC sample loss during simultaneous MDMA eMMC writes?
Q3 — eMMC offline readout via USB
After the flight I need to read the raw eMMC data on a PC for post-processing.
Can I implement USB MSC using the H743 USB OTG FS on PA11/PA12. The STM32 reads eMMC via SDMMC1 and exposes it as a USB drive. Is it possible ? What component do I need to add ?
Q4 — eMMC raw sector access without filesystem
I am writing raw sectors directly (no FatFS) using HAL_MMC_WriteBlocks_DMA for performance. After plugging via USB MSC, will the PC see the device as a raw disk ? Or does USB MSC require the device to have a valid MBR/partition table?
Thank you for any feedback. I am really not an expert in this domain and I tried my best to gather informations. But I am not 100% sure of what I found as it is a mix of forums answers, datasheets and Claude AI help.
Florian
