Hi. I have been using STM32F1xx for many years. I have a new design that uses two uarts and the ADC peripheral - all using DMA. My question is: is it possible to overload the bus arbiter when there are too many dma transactions going on at the same time?

[stuart239955]

When both UARTS are transmitting & receiving, my ADC conversions (via DMA) sometimes do not complete. If I double clock speed (which I do not want to do in the product), the problem goes away. I cannot see any issues in my code that would cause this. Could it be that the DMA / arbiter has run out of steam?

[TDK]

You can absolutely overload the bus. Most memory actions are sharing the same bus. However, USART isn't a big consumer of data at typical speeds. How much bandwidth are you expecting out of the DMA for the ADC and USART?

[stuart239955]

Hi. Thanks for your reply.

I'm using a STM32F103VE micro at

HCLK / AHB = 36MHz

APB1 = 18MHz

APB2 = 36MHz

I've got 2 UARTS using DMA

one at 187.5kBaud running as fast as possible to a PC (about 17k bytes / second)

other at 115.2 kBaud also running as fast as possible to a sensor (about 10k bytes / second)

ADC is continually converting 4 channels via DMA - clock @ 4.5MHz x 239.5 samples (about 18k conversions / second)

It does look like quite a large bandwidth! As I understand it, the same bus is also used by the CPU, so there's that to add to the mix too.

Do you know of the maximum available?

What happens when the bus is overloaded? I would have thought I got an exception, but nothing. Is that a clue to what's happenning?

As previously mentioned, if I double all the clock speeds, the problem goes away.

I hope that gives you enough information.

Regards,

S

[TDK]

The calculation is not straightforward or documented very well, but is probably in the MB/s for your clock settings.

If the bus is overloaded, the CPU will block until it gets the information it needs, the DMA will wait until it gets access as well, which may cause an underflow/overflow error depending on the nature of the access. I would check for those flags, or debug the system and examine the register values to determine the state of the ADC/UART/DMA and why it's not currently working.

[stuart239955]

Thank you for your answer. I have examined Application note AN2548: 'Using the STM32F0/F1/F3/Gx/Lx Series DMA controller' and am on the same track as you.

So, the answer is that the DMA transfer does not get dropped, it just gets delayed (or blocked). My code is not overloading the bus, I believe the error is in my code. I have just simplified my code (to use low level drivers / registers) and the issue is (for now) resolved. Hopefully, fixed!

Regards

S