2020-07-01 09:57 AM
Please show me my design mistakes. I was guided by AN4488. The electrical circuit is attached in the files below in pdf or jpeg format
Thank you!
Solved! Go to Solution.
2020-07-01 03:41 PM
Values for C12/C13 seem pretty low. Typical values are more like 10-20pF. Going to depend on what X1 is.
L1 seems odd. I can maybe see it being included if there's a long wire between VDD and this board. But if your VDD rail generation is right next to the chip, I'd remove it. If you're trying to filter for analog reasons, then L1 should be between VDD and VDDA. It'll probably run fine like this though.
Seems fine otherwise.
2020-07-01 03:41 PM
Values for C12/C13 seem pretty low. Typical values are more like 10-20pF. Going to depend on what X1 is.
L1 seems odd. I can maybe see it being included if there's a long wire between VDD and this board. But if your VDD rail generation is right next to the chip, I'd remove it. If you're trying to filter for analog reasons, then L1 should be between VDD and VDDA. It'll probably run fine like this though.
Seems fine otherwise.