HCLK and SYSCLK and Cortex-M Core speed

[sholojda]

Hi. I am a little bit confused after reading Reference Manual.

What is the difference beteen HCLK and SYSCLK?

Which clock is used to feed MCU Core?

When we talking about time to execute instruction which clock cycle does it concern?

[Peter BENSCH]

This can probably best be seen with the Clock Configuration View in STM32CubeMX.

SYSCLK is the output of the clock multiplexer, which is clocked by clock sources such as HSI, HSE or PLLCLK. HCLK is then derived from SYSCLK, but by a prescaler of 1:1...1:512.

However, this scheme can vary depending on the STM32 family and use different naming conventions.

Depending on the specific family the MCU core is usually clocked by HCLK. Therefore, when we talk about the time to execute instructions, we talk about the HCLK clock cycle.

Regards

/Peter

[Tesla DeLorean]

Depends on the core, the HCLK (AHBCLK) on the H7's CM7 is slower than the SYSCLK which runs the processor and clocks the DWT CYCCNT

The SYSTICK is normally clocked at SYSCLK/8 or SYSCLK on STM32 designs.

In all cases the Clock Tree should be in the Reference Manual to review the exact plumbing, divider chains, etc.

/**
  * @brief  System Clock Configuration
  *         The system Clock is configured as follow :
  *            System Clock source            = PLL (HSE BYPASS)
  *            SYSCLK(Hz)                     = 400000000 (CPU Clock)
  *            HCLK(Hz)                       = 200000000 (AXI and AHBs Clock)
  *            AHB Prescaler                  = 2
  *            D1 APB3 Prescaler              = 2 (APB3 Clock  100MHz)
  *            D2 APB1 Prescaler              = 2 (APB1 Clock  100MHz)
  *            D2 APB2 Prescaler              = 2 (APB2 Clock  100MHz)
  *            D3 APB4 Prescaler              = 2 (APB4 Clock  100MHz)
  *            HSE Frequency(Hz)              = 8000000
  *            PLL_M                          = 4
  *            PLL_N                          = 400
  *            PLL_P                          = 2
  *            PLL_Q                          = 4
  *            PLL_R                          = 2
  *            VDD(V)                         = 3.3
  *            Flash Latency(WS)              = 4
  * @param  None
  * @retval None
  */ 

[sholojda]

Where sholud I look for information about clocking DWT CYCCNT? In which document it is decribed?

And coming forward, Why Flash Latency time is calculated according to SYSCLK and not to HCLK?

>>The SYSTICK is normally clocked at SYSCLK/8 or SYSCLK on STM32 designs.

This is not always, i thing. Because in f103 and f411SYSTICK is clocked from HCLK according to CubeMX

[Piranha]

DWT is a core peripheral and therefore runs on the same core clock, which is represented with SystemCoreClock variable in CMSIS.

[Tesla DeLorean]

Well my understanding of this predates CubeMX, and comes from the ARM TRM.

Read the Reference Manual, it is usually more authoritative..

[Tesla DeLorean]

STM32 Programming Manual

https://www.st.com/resource/en/programming_manual/cd00228163-stm32f10xxx-20xxx-21xxx-l1xxxx-cortex-m3-programming-manual-stmicroelectronics.pdf

https://developer.arm.com/documentation/ddi0337/h/data-watchpoint-and-trace-unit/dwt-programmers-model

[Piranha]

The image actually shows and tells that the core and SysTick are indeed clocked from HCLK (AHB clock), not SYSCLK.

[Tesla DeLorean]

Getting into a area where I'd have to check what actually happens on the F1, but it's too old to care..

Half of me wants to think the CPU clocks from SYSCLK, but if HCLK isn't DIV1 it's basically going to hobble it.