H745 memory regions, attributes & cache
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2020-03-06 11:43 AM
In the h745 reference manual, the RAM region of memory is write-back while the code region is write-through. According an app note, cache coherency issues can be avoided by using a write-through ram region. In the h7 the sram sections are aliased in the code region.
Does this mean that i can simply use the aliased addresses to get write-through D2 ram access?
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STM32H7 Series
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2020-03-07 6:41 AM
As the data will not just sit in memory, but be processed by CPU anyway, both (non-cacheable and clean/invalidate) methods have a performance impact. My experience with zero-copy Ethernet driver for lwIP shows that clean/invalidate is much faster, because it allows CPU to cache the data while processing it before transmission and after reception.
As for difficulties getting clean/invalidate right...
- Use up to date CMSIS-Core headers from ARM, not ST's outdated ones with deficient cache management functions.
- Use only ***_by_Addr() clean/invalidate functions.
- Do invalidation only on buffers aligned and sized to cache line size - __SCB_DCACHE_LINE_SIZE.
- Do cleaning on any buffers.
Not so difficult IMHO... :)

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