GPIO current sink capability when configured as pull-up and pin voltage > Vdd + 0.3 V

[GMade]

Hello,

I'm using the STM32L4A6RG and I'm interested in the exact behavior / rating of a GPIO-pin when configured as pull-up. The datasheet says, that if configured as pull-up, the maximum voltage allowed on that pin is Vdd + 0.3 V. That means there is a PN junction (FET used as pulll-up resistor) between the GPIO-pin and the Vdd rail.

How much current can be safely tolerated on that junction if the pin voltage is > Vdd + 0.3 V?

Thanks in advance!

Regards,

Guenther

[waclawek.jan]

I am not ST, but as the pullup is said to be implemented as a transistor in series with a limiting resistor (or a structure which acts as such), and as this combination can sustain 3V while open, I'd guess it can sustain current imposed by same amount of voltage in the opposite direction, too.

I may be terribly mistaken though =)

JW

[oleksandr.karbivsky]

Hi. Datasheet says:

Page 125 >> "4. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled." (It is for 5V tolerant pins).

Page 127 >> "For operation with voltage higher than Min (VDD, VDDA, VDDIO2, VDDUSB, VLCD) +0.3 V, the internal Pull-up and Pull-Down resistors must be disabled."

Page 181 >>> "The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or source up to ± 20 mA (with a relaxed VOL/VOH)."

[GMade]

Hello Jan and Oleksandr,

thanks for your answers!

@Community member​ : The thing with MOSFETs is that they normally act as a diode in parallel, so I'm quite sure, that it won't take 3 V in the other direction (there is also a footnote in the datasheet Page 125).

@oleksandr.karbivsky​ : I know these passages in the datasheet and the citate on Page 181 refers to a driving output (not configured as pull-up / pull-down).

Since I'm designing a safety HW I need a dedicated information directly from ST (sorry, that I forgot to mention that in my first post :see_no_evil_monkey: ).

About the use case: This is not normal operation, I'm just investigating what happens if in case of specific HW failures. I have to ensure that the µC does not get damaged at all.

regards,

Guenther

[waclawek.jan]

Guenther,

> Since I'm designing a safety HW I need a dedicated information directly from ST

This is a primarily user-driven forum, with just casual ST presence. You need to contact ST directly.

JW