fsmc timing

[elec_st]

Posted on January 06, 2014 at 15:50 how he calculate this So, we will have the following FSMC timings: ? Address setup time: 0x1 ? Address hold time: 0x0 ? Data setup time: 0x5 #too-vague

[Tesla DeLorean]

Posted on January 06, 2014 at 16:01

Your part is what? Clocking at what?

[elec_st]

Posted on January 06, 2014 at 18:16

Your part is what? Clocking at what?

i use stm32f4 discovery at 168MHz  but i want to know how he calculate this ?

[Tesla DeLorean]

Posted on January 06, 2014 at 19:31

You've selectively quoted the

http://www.st.com/st-web-ui/static/active/en/resource/technical/document/application_note/CD00201397.pdf

for an STM32F1 series part. One running at 72 MHz (13.8 ns period). The cycle time needs to be >100 ns The 36 ns comes from an earlier working of the timings in the document The cycle settings for the signals will be in quanta of the bus clock, and need to meet the minimum requirements of the memory device being attached. You'll want to review the reference manual for the STM32F4 parts to understand the FSMC bus, and the timing parameters. For a 168 MHz device the FSMC is probably going to be clocking at 84 MHz (11.9 ns period)

[elec_st]

Posted on January 06, 2014 at 22:32

thank you please correct me if i wrong

((ADDSET + 1) + (DATAST + 1)) × HCLK = 100 (for write cycle only as we only write to the LCD) DATAST × 13.8 = 50 The DATAST must verify: DATAST = ((tACC + tAS ) + 36)/HCLK – ADDSET – 4 ------------------------------------------------------------------------ ((10ns + 1) + (10ns + 1)) ×13.8ns = 303.6 DATAST × 13.8 = 50 The DATAST must verify: DATAST = ((100ns + 10ns ) + 36)/13.8ns –10ns – 4=-3.42

[Tesla DeLorean]

Posted on January 06, 2014 at 23:13

ADDSET  and DATAST are in units of clock quanta (ie periods of 13.88 ns for a 72 MHz clocking source). The +1 is because the parameters programmed into the FSMC are in the form N-1, there is at least 1 clock in each of these phases of the bus transaction.

[elec_st]

Posted on January 07, 2014 at 02:52

in data sheet i read this

''Several prescalers allow the configuration of the three AHB buses, the high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the three AHB buses is 168 MHz while the maximum frequency of the high-speed APB domains is 84 MHz. The maximum allowed frequency of the low-speed APB domain is 42 MHz.'' the fsmc clock is 84mhz or a168mhz ?

[Tesla DeLorean]

Posted on January 07, 2014 at 10:29

The Reference Manual is where you want to look, the F4 is not the same as the F1. The FSMC unit may well still clock at 168 MHz, but the external pins can't go >100MHz. The minimum clock division ratio for the external bus is 2. You'll need to review the manual section on FSMC to understand which clocks are in 168 MHz ticks, and those in 84 MHz (or slower) ticks.

Look at some LCD panel configurations for F4 examples, or F2 ones, they will be more relevant than F1 ones.

[jiazhe]

Posted on August 24, 2015 at 06:28

Sorry,

If I use stmf427 controller and fmc bus to control MT29F1G08ABAEAWP nand flash. Should I use the fmc timing equations in documnet http://www.st.com/st-web-ui/static/active/jp/resource/technical/document/application_note/DM00129600.pdf page 34 If I can't use this equations, where can I get the correct equations? Thanks for your reply!

[Tesla DeLorean]

Posted on August 24, 2015 at 07:05

The mechanics of the external bus FSMC/FMC is very similar across the STM32 line but the F4 Reference Manual will give more specific information about what's salient to the part you're using than an App Note for the F3 series, right?

Overview stuff 

http://web.eece.maine.edu/~hummels/classes/ece486/docs/STM32F4-Technical-Training.pdf