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Tomas Hamouz
Tomas Hamouz
Associate III
September 27, 2018
Question

FSMC Timing on STM32L4R5

  • September 27, 2018
  • 2 replies
  • 1019 views

I have LCD connected to FSMC, 16bit parallel interface.

It works, but all signals are twice slower.

SYSCLK is 120MHz (checked using MCO), HCLK divider is 1 (checked with debugger).

Timers TIM2, TIM3 and TIM4 give expected results, so the system clocks are probably setup correctly.

Write timing, using extended mode:

 WriteTiming.AddressSetupTime = 0; 

 WriteTiming.AddressHoldTime = 1;  

 WriteTiming.DataSetupTime = 4;   

 WriteTiming.DataHoldTime = 3;     

 WriteTiming.BusTurnAroundDuration = 8;     

 WriteTiming.CLKDivision = 2;                  

 WriteTiming.DataLatency = 2;                  

 WriteTiming.AccessMode = FMC_ACCESS_MODE_A;

Write cycle should be 66.6 ns, in fact it is cca 135 ns.

If I change timing to

  WriteTiming.DataSetupTime = 2;   

  WriteTiming.DataHoldTime = 1;     

 WriteTiming.BusTurnAroundDuration = 4

I get the original expected speed.

What else should I check?

Tomas

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    2 replies

    waclawek.jan
    waclawek.jan
    Super User
    September 27, 2018

    Ahoj Tomáš,

    My calculator says, that (4 + 3 + 1 + 8)/120MHz = 133ns.

    It also says that (2 + 1 + 1 + 4)/120MHz = 67ns.

    What exactly is the problem?

    JW

    Tomas Hamouz
    Tomas HamouzAuthor
    Associate III
    October 1, 2018

    Aaah, thank you.

    That was my misunderstanding of timing parameters of FSMC.

    In the display DS, there are parameters:

    tWRlow = 15ns

    tWRhigh = 15ns

    write cycle = 66ns

    The Low and High values are minimal values, at least one of them must be wider to match the whole cycle interval.

    So I considered the Bus Turnaround parameter in FSMC in the same manner - it is "minimal sum of partial timing parametrs". But the STM32 DS says "to add a delay at the end of current read or write

    transaction to next transaction on the same bank".

    Once again, thanks for opening my eyes :)

    Tomáš

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