FSMC and DMA causing dma error

[giles]

Posted on December 09, 2008 at 11:34

FSMC and DMA causing dma error

[16-32micros]

Posted on May 17, 2011 at 12:51

Hi Tibo, Giles,

I will follow this interesting case about DMA and FSMC with my design mates and let you posted on the progress once we get the required data for you. Cheers, STOne-32.

[16-32micros]

Posted on May 17, 2011 at 12:51

Dear giles, tibo, all,

The limitation is confirmed in our silicon, This update is already requested and will be available in our (High density) errata in the coming days. Description of the limitation : -------------- Multi-master access are not supported on the FSMC memory map (address space from 0x60000000-0xA0000FFF), Multi-master means: Dma1 / Dma2 or Dma1 / CPU or Dma2 / CPU. When multi-access are performed on this address space a dummy error could be generated on the bus leading to either a CPU fail (Bus-fault interrupt) or a DMA fail (error, transfer is stopped). Workaround : ------------ If several masters (CPU, DMA1, DMA2) need to access the FSMC, the user must ensure that the accesses are not concurrent by software and should be sequential. Cheers, STOne-32. [ This message was edited by: STOne-32 on 24-12-2008 14:00 ]

[tibo]

Posted on May 17, 2011 at 12:51

hi ST1,

here is an open question from

http://www.st.com/mcu/forums-cat-7268-23.html

: The FSMC interface has a 16 * 32 bit write buffer. How can this buffer flushed by / sync with the program (by DMB/DSB??)? Or is it possible to disable the buffer? Perhaps it has something to do with the dma problem and you can discuss (and answer) this with your engineers too.

[tibo]

Posted on May 17, 2011 at 12:51

Hi St1,

there is still one essential question open: how is it possible to flush / sync the FSMC buffer (16 word) with the program? Can I use DMB/DSB for this? Or is there a different way to be sure, that all written data by the program is really written out of the buffer? In our application we have a FPGA with dual ported SRAM connected to the FSMC.