Force a timer to interrupt as soon as possible

[jean]

Hello,

I have a timer TIM2 interrupting every 2ms (that's working).

When I receive SPI data from SPI3_IRQHandler, I want to launch the interrupt of this timer TIM2_IRQHandler as soon as possible (eg in the next 10us).

Then, the timer will continue to interrupt every 2ms by itself.

How is it possible?

(i'm working on a STM32H743)

Thanks a lot, have a nice day!

Jean

[TDK]

You can force an update event with the EGR register:

TIM2->EGR = TIM_EGR_UG;

[jean]

Thanks!

Is there a way to force the interupt in a few us, for example in 1000 CNT (timer count frequency) ?

[TDK]

Set the counter to ARR-1000.

[jean]

Thanks, that is working perfectly!

I wonder what is going on if I force the TIM2 to restart when this timer is already running and processing its functions? (my TIM2 processing time is about 1ms)

Does it restart it to its beginning, without ending its process?

[waclawek.jan]

> I wonder what is going on if I force the TIM2 to restart

What exactly do you mean by "force TIM2 to restart", in terms of TIM registers?

JW

[jean]

• the TIM2 is working, processing its functions
• from another process, I set TIM2->EGR = TIM_EGR_UG (to force the TIM2 to interrupt now) or I set TIM2->CNT =  ARR-1000 (to force the TIM2 to interrupt in a few us)

Does the TIM2 will end its process, and then interrupt and process again its functions? (this is what I need)

[waclawek.jan]

I am not sure what do you mean by "TIM2 processing its functions".

TIM2 - as all timers - is one countern (with a prescaler), several capture/compare units, the slave-controller unit (processing input signals) and the output signals logic. This all works in parallel all the time.

Setting TIMx_EGR.UG generates an Update signal. This reloads (resets) the counter and sets the TIMx_SR.UIF; if TIMx_DIER.UIE is set it triggers an interrupt; if TIMx_DIER.UDE is set it triggers a DMA transfer. The exact behaviour is more complex but this is the gist of it.

Setting TIMx_CNT to any value does exactly that - in the cycle when write occurs, TIMx_CNT has the value it has been assigned to; then it continues to count from that value (if enabled by TIMx_SR1.CEN).

Functionality of timer is described in the TIM chapter of RM.

JW

[TDK]

The timer increments at a regular rate. Setting UGR sets the counter to 0 and generates an update event. Setting CNT to a value doesn't do anything but change the counter, but setting it to ARR - 1000 will mean it will generate an update event in 1000 ticks.

There is no timer process to end or interrupt. It's a simple timer which increments at a fixed rate. If you have things tied to the update interrupt, those will be unchanged if already executing and will be triggered again at the next update event.

[jean]

Okay thanks, i THINK I understand 🙂

So in my case, after updating the counter, the TIM2 will continue to execute its code if already running (tied inside the TIM2_IRQHandler). And when the code inside TIM2_IRQHandler is done, it will be trigged again and execute the code inside TIM2_IRQHandler.

Thanks for your words!