For STM32F407 how to set PLL as the source of SYSCLK and to see it on pin MCO1 o

[kashubadmitry]

Posted on November 16, 2016 at 09:44

Hi! I wrote program for STM32F407, where I set PLL as the source of SYSCLK and want to see it on pin MCO1.

The program is:#include ''stm32f4xx.h''uint32_t i, temp;int main(){//config clockRCC->CR=RCC_CR_HSION;while (!(RCC->CR&RCC_CR_HSIRDY));RCC->APB1ENR=RCC_APB1ENR_PWREN; PWR->CR|= PWR_CR_VOS; RCC->PLLCFGR=RCC_PLLCFGR_PLLSRC_HSI;RCC->PLLCFGR|=0x00000F08;//n=60, m=8, hs=8 MHz, p=2RCC->CR|=RCC_CR_PLLON;while (!(RCC->CR&RCC_CR_PLLRDY));FLASH->ACR|=FLASH_ACR_LATENCY_5WS;RCC->CFGR|= (RCC_CFGR_PPRE2_DIV2|RCC_CFGR_PPRE1_DIV4);RCC->CFGR|= RCC_CFGR_SW_PLL; //enable gpio, usart6, macRCC->AHB1ENR=RCC_AHB1ENR_GPIOAEN;//vkl takt port//config type GPIOGPIOA->MODER|=GPIO_MODER_MODER8_1;//GPIOA->OSPEEDR=GPIO_OSPEEDER_OSPEEDR8;RCC->CFGR|=RCC_CFGR_MCO1;while (1);}Impulses on MCO1 are wrong!What must I do to solve the problem? Thank You!

[waclawek.jan]

Posted on November 16, 2016 at 12:07

How wrong?

What instrument do you use to verify it? Why did you comment out the pin's speed setting? Did you observe the PLL input/output frequency limits? JW

[Tesla DeLorean]

Posted on November 16, 2016 at 16:16

I'm not going to wade into the register mess of OR'ing everything together...

Clean concise SPL example..

void ClockMCO(void)
{
GPIO_InitTypeDef GPIO_InitStructure;
/* Enable GPIOs clocks */
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE);
/* Enable SYSCFG clock */
RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
/* Configure MCO (PA8) */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL ;
GPIO_Init(GPIOA, &GPIO_InitStructure);
GPIO_PinAFConfig(GPIOA, GPIO_PinSource8, GPIO_AF_MCO); // Should be default
/* Output PLL/2 clock on MCO pin (PA8), you could try /1 if below 100 MHz */
RCC_MCO1Config(RCC_MCO1Source_PLLCLK, RCC_MCO1Div_2);
}