Hi,
Connect a 32-bit PSRAM to FMC bank 1.
For single WRITE ACCESS, I understand that FMC D [31: 0] and FMC NBL [3:1] are determined by the AIX data size and bit1 and bit0 of the Memory map address, is that correct?
PSRAM WRITE ACCESS (single transfer)
(1) AIX DATA = 8bit
ADDRESS [1: 0] = 00: FMC_D [7: 0] = valid data, FMC_NBL [0] = 1
ADDRESS [1: 0] = 01: FMC_D [15: 8] = valid data, FMC_NBL [1] = 1
ADDRESS [1: 0] = 10: FMC_D [23:16] = valid data, FMC_NBL [2] = 1
ADDRESS [1: 0] = 11: FMC_D [31:24] = valid data, FMC_NBL [3] = 1
(2) AIX DATA = 16bit
ADDRESS [1: 0] = 00: FMC_D [15: 0] = valid data, FMC_NBL [1: 0] = 11
ADDRESS [1: 0] = 10: FMC_D [31:16] = valid data, FMC_NBL [3: 2] = 11
(3) AIX DATA = 32bit
ADDRESS [1: 0] = 00: FMC_D [31: 0] = valid data, FMC_NBL [3: 0] = 1111
See also the following table.
Akihiro T
