FMC: Burst access fail with continuous clock ?

[ranran]

Hello,

We are struggling for a while with bank2 access in continuous clock.

We are using FPGA connected to bank2 in FMC bus.

We work with FIFO access in FPGA (a single address for the FIFO)

Single register access works fine, but with burst access there are issues:

It seems that burst write is OK, but reading of 4 16-bit registers returns only 2 values.

We verified with signalTap that FPGA try to output 4 values, which means that the "problem" is probably related to MCU, and not FPGA.

Some additional notes:

1. We had to change bank1 (nor flash) from asynchronous to continuous clock, because datasheet states that bank1 must be in continuous clock if any other bank need to be in continuous clock.
2. Datasheet say that only 4 16-bit address access is allowed, and that's is what we try to do.

Is there any idea about this behavior ?

Regards,

ranran

[Tesla DeLorean]

>>which means that the "problem" is probably related to MCU, and not FPGA

The alternate interpretation would be that the FPGA isn't meeting the expectations of the MCU/FMC. The former may be easier to sequence properly if the bus signals are doing what the RM describes.

What does the signalling look like on a Logic Analyzer? Does the FPGA setup its data outputs early enough for the MCU to latch those values?

[ranran]

Hi,

The signal in logic analyzer looks correct, and we don't understand why MCU seems to miss 2 of 4 registers.

Do you have any hint how we can debug this or anyhing which can explain why it fails ?

Thanks