Hi,Master:
I have the following questions about flash introduction in the manual (DM00091010):
Question 1:
The manual(3.2.2) says:
"On the contrary, during a program/erase operation to the Flash memory, any attempt to read the Flash memory will stall the bus. The read operation will proceed correctly once the
program/erase operation has completed. This means that code or data fetches cannot be
made while a program/erase operation is ongoing"
-Here "This means that code or data fetches cannot be made while a program/erase operation is ongoing", my question is that it seems that the instruction fetching is also suspended? If it is, then the cpu does not execute instructions, so does the interrupt routine also delay execution? What does this sentence really mean？
Question 2:
Latency
000: Zero wait state, if SYSCLK ≤ 24 MHz
001: One wait state, if 24 MHz <SYSCLK ≤ 48 MHz
-If the CPU frequency is 48Mhz, Latency = 1
At this time, when does the cpu wait for 1 cycle?
a. If the prefetch buffer is enabled, does the cpu wait for a cycle when it is empty?
b. If the prefetch buffer is disabled, when does the cpu wait for 1 cycle?
thank you very much!
