STM32H753: How is an ECC in the L1 caches reported

[DBine.1]

Hi,

I'm currently working on a STM32H753. I'm trying to figure out how an ECC error upon a cache look up is reported. The cortex M7 reference manual doesn't provide much info in that regards with the following text:

Each cache can also be configured with ECC. If ECC is implemented and enabled, then the tags

associated with each line, and data read from the cache are checked whenever a lookup is

performed in the cache and, if possible, the data is corrected before being used in the processor.

A full description of ECC error checking and correction is beyond the scope of this document.

Contact ARM if you require more information.

I'm expecting a bus fault to be reported but I'm not able to find a documentation with that information. I'm waiting for an answer from ARM but is there anything specific to the implementation made by ST that would impact how this fault would be reported ?

Kind Regards,

David

[Amel NASRI · Accepted solution]

Hi @DBine.1​ ,

There is a dedicated application note which describes the error correction code (ECC) management and implementation on STM32H7 Series.

It is AN5342. Please let me know if this answers your request. If yes, you can select my answer as best.

If you think that there is still some more details, it will be interesting to share them with us. This will help to improve this document's document.

Amel