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Fastest ADC measures with DMA

0xfab
Associate

I'm using a Nucleo-G474RE to measure a signal via ADC1.

ADC measures are triggered by TIM2, then transferred via DMA1 into a large buffer (60KB).

When the buffer is full an interrupt is generated and I give the DMA another 60KB buffer.

After that, everything is stopped and I upload the buffers to the PC via LPUART1.

Finally I check the result with a 100Hz sinusoidal input.

So far so good, I can set TIM2 up to 3.86333MHz, but anything above will result in a sub-sampling output (between 2 and 3Msmpl/s).

That's 44 cycles (clock is 170MHz on all buses). I was expecting to go higher, since I set the ADC measure time to its minimum (2.5 cycles sampling time, 8 bits, no filtering), so a measure should take ~11 cycles, plus the DMA transfer (1 byte of data), so maybe 20 cycles per measure.

No transfer error or ADC overrun is reported, and nothing else runs during the measures.

My question is: what could possibly eat up 24 cycles per measure, and how to maximize the number of ADC measures per second?

1 ACCEPTED SOLUTION

Accepted Solutions
MasterT
Senior III

11 cycles for adc's clock. Usually adc driven by PCL /4, so 44 is about right. DMA transfer should not be counted, it goes during next conversion in background. 

I succsesfully tested adc on G474 with clock 168 MHz (x3 above datasheet max), 12-bits 2.5 S/H, 11.2 MSPS.

The only uCPU that capable to run at this high overdrive w/o significant lowering in ENOB (~7 bits). Board nucleo-G474.

So, check up clock, two options - sync and async from another PLL. High speed 'd demand fast differential buffer for adc, LMH6612 or THS7373 - low cost but excellent for a task

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2 REPLIES 2
MasterT
Senior III

11 cycles for adc's clock. Usually adc driven by PCL /4, so 44 is about right. DMA transfer should not be counted, it goes during next conversion in background. 

I succsesfully tested adc on G474 with clock 168 MHz (x3 above datasheet max), 12-bits 2.5 S/H, 11.2 MSPS.

The only uCPU that capable to run at this high overdrive w/o significant lowering in ENOB (~7 bits). Board nucleo-G474.

So, check up clock, two options - sync and async from another PLL. High speed 'd demand fast differential buffer for adc, LMH6612 or THS7373 - low cost but excellent for a task

0xfab
Associate

Thanks a lot for your quick answer.

Indeed, I missed the CKMODE bits. Setting DIV2 allows me to go higher as expected, without changing the look of the output much.

Setting DIV1 however produces a slightly ugly output, regardless of the sampling time.

I guess I'll adjust it depending of the desired sampling frequency.