['F446 documentation] RCC - using odd output dividers on PLLs

[waclawek.jan]

Posted on January 18, 2018 at 00:18

Some PLL/PLLI2S/PLLSAI outputs (namely R and Q) allow odd dividers, which results in assymetric clock waveform (the extreme is divider=3, with duty cycle 2:1). The Q output of PLLI2S and PLLSAI further goes through a divider, but that may be 'transparent' and have odd division ratio too.

Such assymetric clock can then be fed for example to SAI, where,

if SAI used to generate SPDIF and clock is not divided (SAIx_CR1.MCKDIV=0), is used directly to generate the biphase modulated output. That output is then incorrect.

Also in FREE mode of SAI, if assymetric MCLK is output and fed as master clock to external circuit (CODEC), some of the attached CODECs may work incorrectly.

If I haven't overlooked something and the above is all true, please add a comment/warning to RM, to the RCC chapter, both to description of related PLLs' dividers, and to RCC_DCKCFGR.SAIxSRC description.

And, of course, into the Interconnection chapter, which I hope will appear in RM0390 too.

There may be other peripherals impacted, I am not going to investigate this further.

Of course, as most if not all other of my ['F446 documentatino] rants, this may be relevant for other STM32 models/subfamilies too.

JW

[waclawek.jan]

Posted on January 25, 2018 at 22:16

EDIT: Strikethrough above in light of

https://community.st.com/0D50X00009XkaCESAZ

i.e. that SAI in SPDIF-Tx mode divides the clock by 2 probably at the modulator stage.

The potential problem with external ICs connected to output clock still remains.

OTOH, in 'F446, PLL_R can be used as SYSCLK, so there virtually all peripherals may be impacted - most of them employ some form of input clock division, but IMO it's still worth to put in a few cautionary words.

JW